STAC9704 Datasheet, PDF (17/49 Pages) Hynix Semiconductor – Multimedia Audio Codec for AC97

SigmaTel, Inc.
STAC9704/7
Within slot 0 the first bit is a global bit (SDATA_IN slot 0, bit 15) which flags whether the
STAC9704/7 is in the "Codec Ready" state or not. If the “Codec Ready” bit is a 0, this indicates that
STAC9704/7 is not ready for normal operation. This condition is normal following the de-assertion of
power on reset, for example, while STAC9704/7’s voltage references settle. When the AC-link "Codec
Ready" indicator bit is a 1, it indicates that the AC-link and STAC9704/7 control/status registers are in
a fully operational state. The AC'97 controller must further probe the Powerdown Control Status
Register (refer to Mixer Register section) to determine exactly which subsections, if any, are ready.
Prior to any attempts at putting STAC9704/7 into operation the AC'97 controller should poll the first bit
in the audio input frame (SDATA_IN slot 0, bit 15) for an indication that STAC9704/7 has become
"Codec Ready". Once the STAC9704/7 is sampled "Codec Ready", the next 12 bit positions sampled
by the AC'97 controller indicate which of the corresponding 12 time slots are assigned to input data
streams, and that they contain valid data. The following diagram illustrates the time slot based AC-link
protocol.
Tag Phase
Figure 8: STAC9704/7 Audio Input Frame
Data Phase
20.8 uS (48 kHZ)
SYNC
12.288 MHz
BIT_CLK
SDATA_IN
valid
Frame
slot1
slot2
slot(12) "0" "0" "0" 19
"0"
End of previous audio frame
Time Slot "Valid" Bits
("1" = time slot contains valid PCM data)
Slot 1
19
"0" 19
"0"
Slot 2
Slot 3
19
"0"
Slot 12
A new audio input frame begins with a low to high transition of SYNC. SYNC is synchronous to the
rising edge of BIT_CLK. On the immediately following falling edge of BIT_CLK, STAC9704/7
samples the assertion of SYNC. This falling edge marks the time when both sides of AC-link are aware
of the start of a new audio frame. On the next rising of BIT_CLK, the STAC9704/7 transitions
SDATA_IN into the first bit position of slot 0 ("Codec Ready" bit). Each new bit position is presented
to AC-link on a rising edge of BIT_CLK and subsequently sampled by the AC'97 controller on the
following falling edge of BIT_CLK. This sequence ensures that data transitions, and subsequent
sample points for both incoming and outgoing data streams are time aligned.
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10/02/98