HY5DU56422AT Datasheet, PDF (35/36 Pages) Hynix Semiconductor – 256M-S DDR SDRAM

HY5DU56422A(L)T
HY5DU56822A(L)T
HY5DU561622A(L)T
CAPACITANCE (TA=25^oC, f=100MHz )
Parameter
Input Clock Capacitance
Delta Input Clock Capacitance
Input Capacitance
Delta Input Capacitance
Input / Output Capacitance
Delta Input / Output Capacitance
Pin
CK, /CK
CK, /CK
All other input-only pins
All other input-only pins
DQ, DQS, DM
DQ, DQS, DM
Symbol
Min
Max
Unit
CI1
2.0
3.0
pF
Delta CI1
-
0.25
pF
CI1
2.0
3.0
pF
Delta CI2
-
0.5
pF
CIO
4.0
5.0
pF
Delta CIO
-
0.5
pF
Note :
1. VDD = min. to max., VDDQ = 2.3V to 2.7V, VODC = VDDQ/2, VOpeak-to-peak = 0.2V
2. Pins not under test are tied to GND.
3. These values are guaranteed by design and are tested on a sample basis only.
OUTPUT LOAD CIRCUIT
VTT
RT=50Ω
Output
Zo=50Ω
CL=30pF
VREF
Rev. 0.4/ May. 02
35