HY5DU56422AT Datasheet, PDF (18/36 Pages) Hynix Semiconductor – 256M-S DDR SDRAM

HY5DU56422A(L)T
HY5DU56822A(L)T
HY5DU561622A(L)T
7. Issue 2 or more Auto Refresh commands.
8. Issue a Mode Register Set command to initialize the mode register with bit A8 = Low.
Power-Up Sequence
VDD
VDDQ
tVTD
VTT
VREF
/CLK
CLK
CKE
CMD
tIS tIH
NOP
PRE
EMRS
MRS
NOP
PRE
AREF
MRS
DM
ADDR
A10
BA0,BA1
CODE
CODE
CODE
CODE
CODE
CODE
CODE
CODE
CODE
DQS
DQ’s
T=200usec
tRP
tMRD
200 cycles of CK*
tRP
tRFC
Power up
VDD and CK stable
EMRS Set
Precharge All
MRS Set
Reset DLL
(with A8=H)
2 or more MRS Set
Precharge All _{Auto Refresh (with A8=L)}
*200 cycles of CK are required (for DLL locking) before any executable command can be applied.
Rev. 0.4/ May. 02
18