HY5DU56422AT Datasheet, PDF (24/36 Pages) Hynix Semiconductor – 256M-S DDR SDRAM

DC CHARACTERISTICS II (TA=0 to 70 ^oC, Voltage referenced to VSS = 0V)
HY5DU56422A(L)T
HY5DU56822A(L)T
HY5DU561622A(L)T
64Mx4
Parameter Symbol
Test Condition
Speed
-J -M -K -H
One bank; Active - Precharge;
tRC=tRC(min); tCK=tCK(min); DQ,DM and
Operating Current
IDD0 DQS inputs changing twice per clock cycle;
105
95
address and control inputs changing once
per clock cycle
One bank; Active - Read - Precharge;
Operating Current
IDD1
Burst=2; tRC=tRC(min); tCK=tCK(min);
address and control inputs changing once
150
130
per clock cycle; IOUT=0mA
Precharge Power
Down Standby
Current
IDD2P
All banks idle; Power down mode; CKE=Low,
tCK=tCK(min)
20
/CS=High, All banks idle; tCK=tCK(min);
Idle Standby Current
IDD2F
CKE=High; address and control inputs
changing once per clock cycle.
50
40
VIN=VREF for DQ, DQS and DM
Active Power Down
Standby Current
IDD3P
One bank active; Power down mode ;
CKE=Low, tCK=tCK(min)
25
/CS=HIGH; CKE=HIGH; One bank; Active-
Active Standby
Current
Precharge; tRC=tRAS(max); tCK=tCK(min);
IDD3N DQ, DM and DQS inputs changing twice per
60
clock cycle; Address and other control inputs
50
changing once per clock cycle
Burst=2; Reads; Continuous burst; One bank
Operating Current
IDD4R
active; Address and control inputs changing
once per clock cycle; tCK=tCK(min);
280
240
IOUT=0mA
Burst=2; Writes; Continuous burst; One
bank active; Address and control inputs
Operating Current
IDD4W changing once per clock cycle;
280
240
tCK=tCK(min); DQ, DM and DQS inputs
changing twice per clock cycle
Auto Refresh Current IDD5 tRC=tRFC(min); All banks active
230
210
Self Refresh Current
IDD6
CKE=<0.2V; External clock on; ^Normal
tCK=tCK(min)
Low Power
3
1.5
Operating Current -
Four Bank Operation
IDD7
Four bank interleaving with BL=4, Refer to
the following page for detailed test condition
305
295
Unit Note
-L
90 mA
120 mA
mA
35 mA
mA
50 mA
180 mA
180 mA
195 mA
mA
mA
295 mA
Rev. 0.4/ May. 02
24