HY5DU56422AT Datasheet, PDF (32/36 Pages) Hynix Semiconductor – 256M-S DDR SDRAM

HY5DU56422A(L)T
HY5DU56822A(L)T
HY5DU561622A(L)T
Parameter
Symbol
DDR266A
Min
Max
Input Setup Time (fast slew rate)
tIS
0.9
-
Input Hold Time (fast slew rate)
tIH
0.9
-
Input Setup Time (slow slew rate)
tIS
1.0
-
Input Hold Time (slow slew rate)
tIH
1.0
-
Input Pulse Width
tIPW
2.2
-
Write DQS High Level Width
tDQSH 0.35
-
Write DQS Low Level Width
tDQSL 0.35
-
Clock to First Rising edge of DQS-In
tDQSS 0.75
1.25
Data-In Setup Time to DQS-In (DQ & DM) tDS
0.5
-
Data-in Hold Time to DQS-In (DQ & DM)
tDH
0.5
-
DQ & DM Input Pulse Width
tDIPW 1.75
-
Read DQS Preamble Time
tRPRE
0.9
1.1
Read DQS Postamble Time
tRPST
0.4
0.6
Write DQS Preamble Setup Time
tWPRES
0
-
Write DQS Preamble Hold Time
tWPREH 0.25
-
Write DQS Postamble Time
tWPST
0.4
0.6
Mode Register Set Delay
tMRD
2
-
Exit Self Refresh to Any Execute Command tXSC
200
-
Average Periodic Refresh Interval
tREFI
-
7.8
DDR266B
Min
Max
0.9
-
0.9
-
1.0
-
1.0
-
2.2
-
0.35
-
0.35
-
0.75
1.25
0.5
-
0.5
-
1.75
-
0.9
1.1
0.4
0.6
0
-
0.25
-
0.4
0.6
2
-
200
-
-
7.8
DDR200
Min
Max
1.1
-
1.1
-
1.1
-
1.1
-
2.5
-
0.35
-
0.35
-
0.75
1.25
0.6
-
0.6
-
2
-
0.9
1.1
0.4
0.6
0
-
0.25
-
0.4
0.6
2
-
200
-
-
7.8
Unit Note
ns _2,3,5,
ns
6
ns _2,4,5,
ns
6
ns 6
CK
CK
CK
ns 6,7,
11,12
ns _,13
ns
CK
CK
CK
CK
CK
CK
CK 8
us
Rev. 0.4/ May. 02
32