HY5DU281622ETP-25 Datasheet, PDF (30/34 Pages) Hynix Semiconductor – 128M(8Mx16) gDDR SDRAM

1HY5DU281622ETP
AC CHARACTERISTICS - I (Continued)
Parameter
Row Cycle Time(Manual Precharge)
Row Cycle Time(Auto Precharge)
Auto Refresh Row Cycle Time
Row Active Time
Row Address to Column Address Delay for Read
Row Address to Column Address Delay
for Write
Row Active to Row Active Delay
Column Address to Column Address Delay
Row Precharge Time
Write Recovery Time
Last Data-In to Read Command
Auto Precharge Write Recovery +
Precharge Time
System Clock Cycle Time
CL=4
CL=3
Clock High Level Width
Clock Low Level Width
Data-Out edge to Clock edge Skew
DQS-Out edge to Clock edge Skew
DQS-Out edge to Data-Out edge Skew
Data-Out hold time from DQS
Clock Half Period
Data Hold Skew Factor
Input Setup Time
Input Hold Time
Write DQS High Level Width
Write DQS Low Level Width
Clock to First Rising edge of DQS-In
Data-In Setup Time to DQS-In (DQ & DM)
Data-In Hold Time to DQS-In (DQ & DM)
DQS falling edge to CK setup time
Symbol
tRC
tRC_APCG
tRFC
tRAS
tRCDRD
4
Min
Max
15
-
17
-
18
-
10
100K
5
-
tRCDWR
3
-
tRRD
3
-
tCCD
1
-
tRP
5
-
tWR
3
-
tDRL
2
-
tDAL
8
-
4
10
tCK
-
-
tCH
0.45
0.55
tCL
0.45
0.55
tAC
-0.6
0.6
tDQSCK
-0.6
0.6
tDQSQ
-
0.4
tQH
tHPmin
-tQHS
-
tHP
tCH/L
min
-
tQHS
-
0.4
tIS
0.75
-
tIH
0.75
-
tDQSH
0.4
0.6
tDQSL
0.4
0.6
tDQSS
0.85
1.15
tDS
0.4
-
tDH
0.4
-
tDSS
0.3
-
5
Min
Max
12
-
13
-
14
-
8
100K
4
-
Unit Note
CK
CK
CK
CK
2
-
CK
2
-
CK
1
-
CK
4
-
CK
3
-
CK
2
-
CK
7
-
CK
-
-
ns
5
10
0.45
0.55
CK
0.45
0.55
CK
-0.65
0.65
ns
-0.55
0.55
ns
-
0.4
ns
tHPmin
-tQHS
-
ns 1,6
tCH/L
min
-
ns 1,5
-
0.45
ns 6
0.6
-
ns 2
0.6
-
ns 2
0.4
0.6
CK
0.4
0.6
CK
0.72
1.28
CK
0.4
-
ns 3
0.4
-
ns 3
0.3
-
CK
Rev. 1.0 / Oct. 2005
30