HY5DU281622ETP-25 Datasheet, PDF(16/34 Page) Hynix Semiconductor

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HY5DU281622ETP-25 Datasheet, PDF (16/34 Pages) Hynix Semiconductor – 128M(8Mx16) gDDR SDRAM

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1HY5DU281622ETP

7. Issue Precharge commands for all banks of the device.

8. Issue 2 or more Auto Refresh commands.

9. Issue a Mode Register Set command to initialize the mode register with bit A8 = Low.

Power-Up Sequence

VDD

VDDQ

VTT

VREF

/CLK

CLK

tVTD

CKE

CMD

LVCMOS Low Level

tIS tIH

NOP

PRE

EMRS

MRS

NOP

PRE

AREF

MRS

ACT

ADDR

CODE

A10

CODE

BA0, BA1

DQS

DQ'S

CODE

T=200usec

Power UP

VDD and CK stable

tRP

tMRD

tRP

tRFC

tMRD

Precharge All

EMRS Set

MRS Set

Reset DLL

(with A8=H)

tXSRD*

Precharge All 2 or more

MRS Set

Auto Refresh (with A8=L)

Non-Read

Command

READ

* 200 cycle(tXSRD) of CK are required (for DLL locking) before Read Command

Note)

1. VTT is not applied directly to the device; however, tVTD should be greater than or equal to zero to avoid device

latch-up. VDDQ, VTT and VREF must be equal to or less than VDD+0.3V. Alternatively, VTT may be 1.35V

maximum during power up, even if VDD/VDDQ are 0V. Once initialized, including self refresh mode, VREF must

always be powered within specified range.

2. The Power Voltage ramp time between initial VDD and VDDmin must be no less than 3ms.

3. The Initial VDD must be maintained under 100mV.

Rev. 1.0 / Oct. 2005

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