HY5DU12422AT Datasheet, PDF (30/33 Pages) Hynix Semiconductor – 512Mb DDR SDRAM

Parameter
Input Pulse Width
Write DQS High Level Width
Write DQS Low Level Width
Clock to First Rising edge of DQS-In
DQS falling edge to CK setup time
DQS falling edge hold time from CK
Data-In Setup Time to DQS-In (DQ & DM)
Data-in Hold Time to DQS-In (DQ & DM)
DQ & DM Input Pulse Width
Read DQS Preamble Time
Read DQS Postamble Time
Write DQS Preamble Setup Time
Write DQS Preamble Hold Time
Write DQS Postamble Time
Mode Register Set Delay
Exit Self Refresh to Any Execute Command
Average Periodic Refresh Interval
HY5DU12422A(L)T
HY5DU12822A(L)T
HY5DU121622A(L)T
Symbol
tIPW
tDQSH
tDQSL
tDQSS
tDSS
tDSH
tDS
tDH
tDIPW
tRPRE
tRPST
tWPRES
tWPREH
tWPST
tMRD
tXSC
tREFI
DDR400 (D4)
Min
Max
2.2
-
0.35
-
0.35
-
0.72
1.28
0.2
0.2
0.4
-
0.4
-
1.75
-
0.9
1.1
0.4
0.6
0
-
0.25
-
0.4
0.6
2
-
200
-
-
7.8
DDR400 (D43)
Min
Max
2.2
-
0.35
-
0.35
-
0.72
1.28
0.2
0.2
0.4
-
0.4
-
1.75
-
0.9
1.1
0.4
0.6
0
-
0.25
-
0.4
0.6
2
-
200
-
-
7.8
-Continue-
Unit Note
ns
6
CK
CK
CK
CK
CK
ns 6,7,11
,
ns 12,13
ns
6
CK
CK
CK
CK
CK
CK
CK
8
us
Note :
1. This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter.
2. Data sampled at the rising edges of the clock : A0~A12, BA0~BA1, CKE, /CS, /RAS, /CAS, /WE.
3. For command/address input slew rate >=1.0V/ns
4. For command/address input slew rate >=0.5V/ns and <1.0V/ns
This derating table is used to increase tIS/tIH in case where the input slew-rate is below 0.5V/ns.
Input Setup / Hold Slew-rate Derating Table.
Input Setup / Hold Slew-rate
Delta tIS
Delta tIH
V/ns
ps
ps
0.5
0
0
0.4
+50
0
0.3
+100
0
Rev. 0.0/Feb. 2003
30