HY5DU12422AT Datasheet, PDF (3/33 Pages) Hynix Semiconductor – 512Mb DDR SDRAM

DESCRIPTION
HY5DU12422A(L)T
HY5DU12822A(L)T
HY5DU121622A(L)T
PRELIMINARY
The HY5DU12422A(L)T, HY5DU12822A(L)T and HY5DU121622A(L)T are a 536,870,912-bit CMOS Double Data
Rate(DDR) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density
and high bandwidth.
This Hynix 512Mb DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the
clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data,
Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are inter-
nally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible
with SSTL_2.
FEATURES
• VDD, VDDQ = 2.5V +/- 0.2V
• All inputs and outputs are compatible with SSTL_2
interface
• Fully differential clock inputs (CK, /CK) operation
• Double data rate interface
• Source synchronous - data transaction aligned to
bidirectional data strobe (DQS)
• x16 device has two bytewide data strobes (UDQS,
LDQS) per each x8 I/O
• Data outputs on DQS edges when read (edged DQ)
Data inputs on DQS centers when write (centered
DQ)
• On chip DLL align DQ and DQS transition with CK
transition
• DM mask write data-in at the both rising and falling
edges of the data strobe
• All addresses and control inputs except data, data
strobes and data masks latched on the rising edges
of the clock
• Programmable /CAS latency 2 / 2.5/ 3 supported
• Programmable burst length 2 / 4 / 8 with both
sequential and interleave mode
• Internal four bank operations with single pulsed
/RAS
• Auto refresh and self refresh supported
• tRAS lock out function supported
• 8192 refresh cycles / 64ms
• JEDEC standard 400mil 66pin TSOP-II with 0.65mm
pin pitch
• Full and Half strength driver option controlled by
EMRS
ORDERING INFORMATION
Part No.
HY5DU12422A(L)T-X*
HY5DU12822A(L)T-X*
HY5DU121622A(L)T-X*
Configuration
128Mx4
64Mx8
32Mx16
Package
400mil
66pin
TSOP-II
* Note : D of speed indicates DDR400.
OPERATING FREQUENCY
Grade
- D4
- D43
CL3
200MHz
200MHz
Remark
(CL-tRCD-tRP)
DDR400 (3-4-4)
DDR400 (3-3-3)
Rev. 0.0 / Feb. 2003
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