HY5DU12422AT Datasheet, PDF (24/33 Pages) Hynix Semiconductor – 512Mb DDR SDRAM

HY5DU12422A(L)T
HY5DU12822A(L)T
HY5DU121622A(L)T
DC CHARACTERISTICS II (TA=0 to 70 ^oC, Voltage referenced to VSS = 0V)
128Mx4
Parameter
Operating Current
Operating Current
Precharge Power Down
Standby Current
Idle Standby Current
Idle Standby Current
Idle Quiet Standby Current
Active Power Down
Standby Current
Active Standby Current
Operating Current
Operating Current
Auto Refresh Current
Self Refresh Current
Operating Current - Four
Bank Operation
Random Read Current
Symbol
Test Condition
Speed
Unit Note
-D4 -D43
One bank; Active - Precharge ; tRC=tRC(min);
IDD0
tCK=tCK(min) ; DQ,DM and DQS inputs changing twice
per clock cycle; address and control inputs changing
150
mA
once per clock cycle
One bank; Active - Read - Precharge;
IDD1 Burst Length=2; tRC=tRC(min); tCK=tCK(min); address
200
mA
and control inputs changing once per clock cycle
IDD2P
All banks idle; Power down mode; CKE=Low,
tCK=tCK(min)
10
mA
IDD2N Vin>=Vih(min) or Vin=<Vil(max) for DQ, DQS and DM
35
mA
/CS=High, All banks idle; tCK=tCK(min);
IDD2F
CKE=High; address and control inputs changing once per
clock cycle.
35
mA
VIN=VREF for DQ, DQS and DM
/CS>=Vih(min); All banks idle; CKE>=Vih(min);
IDD2Q Addresses and other control inputs stable, Vin=Vref for
25
mA
DQ, DQS and DM
IDD3P
One bank active; Power down mode; CKE=Low,
tCK=tCK(min)
12
mA
/CS=HIGH; CKE=HIGH; One bank; Active-Precharge;
tRC=tRAS(max); tCK=tCK(min);
IDD3N DQ, DM and DQS inputs changing twice per clock cycle;
50
mA
Address and other control inputs changing once per
clock cycle
Burst=2; Reads; Continuous burst; One bank active;
IDD4R Address and control inputs changing once per clock
270
cycle; tCK=tCK(min); IOUT=0mA
Burst=2; Writes; Continuous burst; One bank active;
IDD4W
Address and control inputs changing once per clock
cycle; tCK=tCK(min); DQ, DM and DQS inputs changing
270
mA
twice per clock cycle
IDD5 tRC=tRFC(min) - 14*tCK for DDR400 at 200Mhz
300
IDD6
CKE =< 0.2V; External clock on;
tCK=tCK(min)
Normal
Low Power
5
mA
2.5
mA
IDD7
Four bank interleaving with BL=4, Refer to the following
page for detailed test condition
540
mA
4banks active read with activate every 20ns, AP(Auto
Precharge) read every 20ns, BL=4, tRCD=3, IOUT=0
IDD7A mA, 100% DQ, DM and DQS inputs changing twice per
540
mA
clock cycle; 100% addresses changing once per clock
cycle
Rev. 0.0/Feb. 2003
24