HYMP512R728 Datasheet, PDF (3/24 Pages) Hynix Semiconductor – 240pin Registered DDR2 SDRAM DIMMs based on 512 Mb 1st ver.

1240pin Registered DDR2 SDRAM DIMMs
Input/Output Functional Description
Symbol
CK0
Type
IN
CK0
IN
CKE[1:0]
IN
S[1:0]
IN
ODT[1:0]
IN
RAS, CAS, WE IN
Vref
Supply
V_DDQ
Supply
BA[1:0]
IN
Polarity
Positive
Edge
Negative
Edge
Active
High
Active
Low
Active
High
Active
Low
-
Pin Description
Positive line of the differential pair of system clock inputs that drives input to the on-DIMM PLL.
Negative line of the differential pair of system clock inputs that drives input to the on-DIMM PLL.
Activates the DDR2 SDRAM CK signal when high and deactivates the CK signal when low.
By deactivating the clocks, CKE low initiates the Power Down mode or the Self Refresh mode.
Enables the associated DDR2 SDRAM command decoder when low and disables the command
decoder when high. When the command decoder is disabled, new commands are ignored but
previous operations continue. Rank 0 is selected by S0; Rank 1 is selected by S1
On-Die Termination signals.
When sampled at the positive rising edge of the clock. RAS,CAS and WE(ALONG WITH S) define
the command being entered.
Reference voltage for SSTL18 inputs
Power supplies for the DDR2 SDRAM output buffers to provide improved noise immunity. For all
current DDR2 unbuffered DIMM designs, V_DDQ shares the same power plane as V_DD pins.
Selects which DDR2 SDRAM internal bank of four is activated.
During a Bank Activate command cycle, Address input difines the row address(RA0~RA13)
A[9:0],
A10/AP
A[13:11]
DQ[63:0],
CB[7:0]
DM[8:0]
V_DD,V_SS
DQS[17:0]
DQS[17:0]
SA[2:0]
SDA
SCL
VDDSPD
RESET
Par_In
Err_Out
TEST
During a Read or Write command cycle, Address input defines the column address when sam-
pled at the cross point of the rising edge of CK and falling edge of CK. In addition to the column
IN
-
address, AP is used to invoke autoprecharge operation at the end of the burst read or write
cycle. If AP is high., autoprecharge is selected and BA0-BAn defines the bank to be precharged.
If AP is low, autoprecharge is disabled. During a Precharge command cycle., AP is used in con-
junction with BA0-BAn to control which bank(s) to precharge. If AP is high, all banks will be pre-
charged regardless of the state of BA0-BAn inputs. If AP is low, then BA0-BAn are used to define
which bank to precharge.
IN
-
Data and Check Bit Input/Output pins.
IN
Supply
I/O
I/O
IN
I/O
IN
Supply
IN
IN
OUT
Active
High
Positive
Edge
Negative
Edge
-
-
-
DM is an input mask signal for write data. Input data is masked when DM is sampled High coin-
cident with that input data during a write access. DM is sampled on both edges of DQS.
Although DM pins are input only, the DM loading matches the DQ and DQS loading.
Power and ground for the DDR2 SDRAM input buffers, and core logic. V_DD and V_DDQ pins are
tied to V_DD/V_DDQ planes on these modules.
Positive line of the differential data strobe for input and output data
Negative line of the differential data strobe for input and output data
These signals are tied at the system planar to either V_SS or V_DDSPD to configure the serial SPD
EEPROM address range.
This is a bidirectional pin used to transfer data into or out of the SPD EEPROM. A resister may
be connected from the SDA bus line to V_DDSPD on the system planar to act as a pull up.
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected
from SCL to V_DDSPD to act as a pull up on the system board.
Power supply for SPD EEPROM. This supply is separate from the VDD/VDDQ power plane.
EEPROM supply is operable from 1.7V to 3.6V.
The RESET pin is connected to the RST pin on the register and to the OE pin on the PLL. When
low, all register outputs will be driven low and the PLL clocks to the DRAMs and register(s) will
be set to low level (the PLL will remain synchronized with the input clock)
Parity bit for the Address and Control bus(“1”. Odd, “0”.Even)
Parity error found in the Address and Control bus
Used by memory bus analysis tools(unused on memory DIMMs)
Rev. 1.0 / Apr. 2005
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