HYMP512R728 Datasheet, PDF (1/24 Pages) Hynix Semiconductor – 240pin Registered DDR2 SDRAM DIMMs based on 512 Mb 1st ver.

240pin Registered DDR2 SDRAM DIMMs based on 512 Mb 1st ver.
This Hynix registered Dual In-Line Memory Module (DIMM) series consists of 512Mb 1st ver. DDR2 SDRAMs in Fine Ball
Grid Array(FBGA) packages on a 240pin glass-epoxy substrate. This Hynix 512Mb 1st ver. based Registered DDR2
DIMM series provide a high performance 8 byte interface in 133.35mm width form factor of industry standard. It is
suitable for easy interchange and addition.
FEATURES
• JEDEC standard Double Data Rate2 Synchronous
DRAMs (DDR2 SDRAMs) with 1.8V +/- 0.1V Power
Supply
• All inputs and outputs are compatible with SSTL_1.8
interface
• 4 Bank architecture
• Posted CAS
• Programmable CAS Latency 3 , 4 , 5
• OCD (Off-Chip Driver Impedance Adjustment)
• ODT (On-Die Termination)
• Fully differential clock operations (CK & CK)
• Programmable Burst Length 4 / 8 with both sequen-
tial and interleave mode
• Auto refresh and self refresh supported
• 8192 refresh cycles / 64ms
• Serial presence detect with EEPROM
• DDR2 SDRAM Package: 60ball FBGA
• 133.35 x 30.00 mm form factor
• Lead-free Products are RoHS compliant
ORDERING INFORMATION
Part Name
HYMP564R728-E3/C4
HYMP512R728-E3/C4
HYMP512R724-E3/C4
HYMP125R72M4-E3/C4
HYMP564R72P8-E3/C4
HYMP512R72P8-E3/C4
HYMP512R72P4-E3/C4
HYMP125R72MP4-E3/C4
Density
512MB
1GB
1GB
2GB
512MB
1GB
1GB
2GB
Organization
64Mx72
128Mx72
128Mx72
256Mx72
64Mx72
128Mx72
128Mx72
256Mx72
# of
DRAMs
9
18
18
36
9
18
18
36
# of
ranks
1
2
1
2
1
2
1
2
Materials
Leaded
Leaded
Leaded
Leaded
Lead free
Lead free
Lead free
Lead free
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 1.0 / Apr. 2005
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