HYMP512R728 Datasheet, PDF (11/24 Pages) Hynix Semiconductor – 240pin Registered DDR2 SDRAM DIMMs based on 512 Mb 1st ver.

INPUT DC LOGIC LEVEL
Parameter
Symbol
Input High Voltage
Input Low Voltage
V_IH(DC)
V_IL(DC)
INPUT AC LOGIC LEVEL
Parameter
AC Input logic High
AC Input logic Low
Symbol
V_IH(AC)
V_IL(AC)
AC INPUT TEST CONDITIONS
1240pin Registered DDR2 SDRAM DIMMs
Min
V_REF + 0.125
-0.30
Min
V_REF + 0.250
-
Max
V_DDQ + 0.3
V_REF - 0.125
Unit
V
V
Notes
Max
-
V_REF - 0.250
Unit
V
V
Notes
Symbol
V_REF
V_SWING(MAX)
SLEW
Condition
Input reference voltage
Input signal maximum peak to peak swing
Input signal minimum slew rate
Value
0.5 * V_DDQ
1.0
1.0
Units
V
V
V/ns
Notes
1
1
2, 3
Notes:
1. Input waveform timing is referenced to the input signal crossing through the V_REF level applied to the device
under test.
2. The input signal minimum slew rate is to be maintained over the range from V_REF to V_{IH(ac) min} for rising edges
and the range from V_REF to V_{IL(ac) max} for falling edges as shown in the below figure.
3. AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions
and VIH(ac) to VIL(ac) on the negative transitions.
V_SWING(MAX)
delta TF
Falling Slew = ^{VREF - VIL(ac) max}
delta TF
delta TR
V_DDQ
V_IH(ac) min
V_IH(dc) min
V_REF
V_IL(dc) max
V_IL(ac) max
V_SS
Rising Slew = ^{VIH(ac)min - VREF}
delta TR
< Figure : AC Input Test Signal Waveform>
Rev. 1.0 / Apr. 2005
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