HMT351S6AFR8C-G7 Datasheet, PDF (3/42 Pages) Hynix Semiconductor – 204pin DDR3 SDRAM SODIMM

HMT351S6AFR8C
Table of Contents
1. Description
1.1 Device Features and Ordering Information
1.1.1 Features
1.1.2 Ordering Information
1.2 Speed Grade & Key Parameters
1.3 Address Table
2. Pin Architecture
2.1 Pin Definition
2.2 Input/Output Functional Description
2.3 Pin Assignment
3. Functional Block Diagram
3.1 4GB, 512Mx64 Module(2Rank of x8)
4. Absolute Maximum Ratings
4.1 Absolute Maximum DC Ratings
4.2 Operating Temperature Range
5. AC & DC Operating Conditions
5.1 Recommended DC Operating Conditions
5.2 DC & AC Logic Input Levels
5.2.1 For Single-ended Signals
5.2.2 For Differential Signals
5.2.3 Differential Input Cross Point
5.3 Slew Rate Definition
5.3.1 For Ended Input Signals
5.3.2 For Differential Input Signals
5.4 DC & AC Output Buffer Levels
5.4.1 Single Ended DC & AC Output Levels
5.4.2 Differential DC & AC Output Levels
5.4.3 Single Ended Output Slew Rate
5.4.4 Differential Ended Output Slew Rate
5.5 Overshoot/Undershoot Specification
5.5.1 Address and Control Overshoot and Undershoot Specifications
5.5.2 Clock, Data, Strobe and Mask Overshoot and Undershoot Specifications
5.6 Input/Output Capacitance & AC Parametrics
5.7 IDD Specifications & Measurement Condtiions
6. Electrical Characteristics and AC Timing
6.1 Refresh Parameters by Device Density
6.2 DDR3 Standard speed bins and AC para
7. DIMM Outline Diagram
7.1 4GB, 512Mx64 Module(2Rank of x8)
Rev. 0.02 / Apr. 2009
3