HMT351S6AFR8C-G7 Datasheet, PDF (18/42 Pages) Hynix Semiconductor – 204pin DDR3 SDRAM SODIMM

HMT351S6AFR8C
5.4.2 Differential DC & AC Output Levels
Below table shows the output levels used for measurements of differential signals.
Symbol
Parameter
DDR3-1066, 1333
Unit
Notes
VOHdiff _{AC differential output high}
(AC) _{measurement level (for output SR)}
+ 0.2 x VDDQ
V
1
VOLdiff _{AC differential output low}
(AC) _{measurement level (for output SR)}
- 0.2 x VDDQ
V
1
1. The swing of °æ 0.2 x VDDQ is based on approximately 50% of the static differential output high
or low swing with a driver impedance of 40ߟ and an effective test load of 25ߟ to VTT = VDDQ/2 at each of
the differential output
5.4.3 Single Ended Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is defined and
measured between VOL(AC) and VOH(AC) for single ended signals as shown in below Table and Figure 5.4.3.
Description
Single ended output slew rate for rising edge
Single ended output slew rate for falling edge
Measured
From
To
VOL(AC)
VOH(AC)
VOH(AC)
VOL(AC)
Defined by
VOH(AC)-VOL(AC)
DeltaTRse
VOH(AC)-VOL(AC)
DeltaTFse
Note:
Output slew rate is verified by design and characterisation, and may not be subject to production test.
D e lta T F se
D elta T R se
vOH (AC)
VÕ
vO L(A C )
< Figure 5.4.3: Single Ended Output Slew Rate Definition >
Rev. 0.02 / Apr. 2009
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