HY5DU283222AF Datasheet, PDF (28/32 Pages) Hynix Semiconductor – 128M(4Mx32) GDDR SDRAM

HY5DU283222AF
Parameter
Symbol
Input Setup Time
tIS
Input Hold Time
tIH
Write DQS High Level
Width
tDQSH
Write DQS Low Level
Width
tDQSL
Clock to First Rising edge
of DQS-In
tDQSS
Data-In Setup Time to
DQS-In (DQ & DM)
tDS
Data-In Hold Time to
DQS-In (DQ & DM)
tDH
DQS falling edge to CK
setup time
tDSS
DQS falling edge hold
time from CK
tDSH
Read DQS Preamble Time tRPRE
Read DQS Postamble
Time
tRPST
Write DQS Preamble
Setup Time
tWPRES
Write DQS Preamble Hold
Time
tWPREH
Write DQS Postamble
Time
tWPST
Mode Register Set Delay
tMRD
Exit Self Refresh to Any
Execute Command
tXSC
Power Down Exit Time
tPDEX
Average Periodic Refresh
Interval
tREFI
28
Min Max
0.75
-
0.75
-
0.4
0.6
0.4
0.6
0.85 1.15
0.35
-
0.35
-
0.3
-
0.3
-
0.9
1.1
0.4
0.6
0
-
0.35
-
0.4
0.6
2
-
200
-
2tCK
+ tIS
-
-
7.8
33
Min Max
0.75
-
0.75
-
0.4
0.6
0.4
0.6
0.85 1.15
0.35
-
0.35
-
0.3
-
0.3
-
0.9
1.1
0.4
0.6
0
-
0.35
-
0.4
0.6
2
-
200
-
2tCK
+ tIS
-
-
7.8
36
Min Max
0.75
-
0.75
-
0.4
0.6
0.4
0.6
0.85 1.15
0.4
-
0.4
-
0.3
-
0.3
-
0.9
1.1
0.4
0.6
0
-
0.35
-
0.4
0.6
2
-
200
-
1tCK
+ tIS
-
-
7.8
4
Min Max
0.75
-
0.75
-
0.4
0.6
0.4
0.6
0.85 1.15
0.4
-
0.4
-
0.3
-
0.3
-
0.9
1.1
0.4
0.6
0
-
0.35
-
0.4
0.6
2
-
200
-
1tCK
+ tIS
-
-
7.8
5
Min Max
Unit Note
0.75
-
ns 2
0.75
-
ns 2
0.4
0.6 CK
0.4
0.6 CK
0.85 1.15 CK
0.45
-
ns 3
0.45
-
ns 3
0.3
-
CK
0.3
-
CK
0.9
1.1 CK
0.4
0.6 CK
0
-
ns
0.35
-
CK
0.4
0.6 CK
2
-
CK
200
-
CK 4
1tCK
+ tIS
-
CK
-
7.8 us
Note :
1. This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter.
2. Data sampled at the rising edges of the clock : A0~A11, BA0~BA1, CKE, /CS, /RAS, /CAS, /WE.
3. Data latched at both rising and falling edges of Data Strobes(DQS0~DQS3) : DQ, DM(0~3).
4. Minimum of 200 cycles of stable input clocks after Self Refresh Exit command, where CKE is held high, is required to complete
Self Refresh Exit and lock the internal DLL circuit of DDR SDRAM.
Rev. 0.7 / Jun. 2004
28