HY5DU283222AF Datasheet, PDF (2/32 Pages) Hynix Semiconductor – 128M(4Mx32) GDDR SDRAM

Revision History
Revision
No.
History
0.1
Defined target spec.
0.11 500MHz speed bin added
0.2
Defined IDD specification
0.3
1) Added 222MHz with CL3 and tCK_max=10ns at HY5DU283222AF-36
2) Changed VDD_min value of HY5DU283222AF-36 from 2.375V to 2.2V
3) Changed AC parameters value of HY5DU283222AF-28/33
- tRCDRD/tRP : from 6 tCK to 5 tCK
- tDAL : from 9 tCK to 8 tCK
- tRFC : from 19 tCK to 17 tCK
4) Changed IDD2N target specification
5) Changed tCK_max value of HY5DU283222AF-33/36 from 6ns to 10ns
0.4
Changed CAS Latency of HY5DU283222AF-28 from CL5 to CL4
0.5
Changed tRAS_max Value from 120K to 100K in All Frequency
0.6
Insert Overshoot/ Under Specification
Insert tDSS/ tDSH parameter
0.7
Added 250MHz/ 200MHz speed bin
HY5DU283222AF
Draft Date Remark
Nov. 2002
Dec. 2002
Feb. 2003
Mar. 2003
June 2003
Aug. 2003
Sep. 2003
Jun. 2004
Rev. 0.7 / Jun. 2004
2