HY5DU283222AF Datasheet, PDF (17/32 Pages) Hynix Semiconductor – 128M(4Mx32) GDDR SDRAM

HY5DU283222AF
MODE REGISTER SET (MRS)
The mode register is used to store the various operating modes such as /CAS latency, addressing mode, burst length,
burst type, test mode, DLL reset. The mode register is program via MRS command. This command is issued by the low
signals of /RAS, /CAS, /CS, /WE and BA0. This command can be issued only when all banks are in idle state and CKE
must be high at least one cycle before the Mode Register Set Command can be issued. Two cycles are required to write
the data in mode register. During the the MRS cycle, any command cannot be issued. Once mode register field is
determined, the information will be held until resetted by another MRS command.
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0
0
RFU
DR TM
CAS Latency
BT
Burst Length
BA0 MRS Type
0
MRS
1
EMRS
A7 Test Mode
0
Normal
1
Vendor
test mode
A8 DLL Reset
0
No
1
Yes
A6 A5 A4 CAS Latency
000
Reserved
001
Reserved
010
Reserved
011
3
100
4
101
5
110
Reserved
111
Reserved
Burst Length
A2 A1 A0
Sequential Interleave
0 0 0 Reserved Reserved
001
2
2
010
4
4
011
8
8
1 0 0 Reserved Reserved
1 0 1 Reserved Reserved
1 1 0 Reserved Reserved
1 1 1 Reserved Reserved
A3
Burst Type
0
Sequential
1
Interleave
Rev. 0.7 / Jun. 2004
17