HY5DU283222AF Datasheet, PDF (25/32 Pages) Hynix Semiconductor – 128M(4Mx32) GDDR SDRAM

HY5DU283222AF
AC CHARACTERISTICS - I (AC operating conditions unless otherwise noted)
Parameter
Symbol
2
Min
Max
Row Cycle Time
tRC
23
-
Auto Refresh Row Cycle Time
tRFC
26
-
Row Active Time
tRAS
16
100K
Row Address to Column Address Delay for Read tRCDRD
7
-
Row Address to Column Address Delay for Write tRCDWR
4
-
Row Active to Row Active Delay
tRRD
4
-
Column Address to Column Address Delay
tCCD
2
-
Row Precharge Time
tRP
7
-
Write Recovery Time
tWR
4
-
Last Data-In to Read Command
tDRL
2
-
Auto Precharge Write Recovery + Precharge Time tDAL
11
-
System Clock Cycle Time
CL=5
CL=4
2
6
tCK
-
-
Clock High Level Width
tCH
0.45
0.55
Clock Low Level Width
tCL
0.45
0.55
Data-Out edge to Clock edge Skew
tAC
-0.45
0.45
DQS-Out edge to Clock edge Skew
tDQSCK
-0.45
0.45
DQS-Out edge to Data-Out edge Skew
tDQSQ
-
0.25
Data-Out hold time from DQS
tQH
tHPmin
-tQHS
-
Clock Half Period
tHP
tCH/L
min
-
Data Hold Skew Factor
tQHS
-
0.25
Input Setup Time
tIS
0.6
-
Input Hold Time
tIH
0.6
-
Write DQS High Level Width
tDQSH
0.45
0.55
Write DQS Low Level Width
tDQSL
0.45
0.55
Clock to First Rising edge of DQS-In
tDQSS
0.85
1.15
Data-In Setup Time to DQS-In (DQ & DM)
tDS
0.35
-
Data-In Hold Time to DQS-In (DQ & DM)
tDH
0.35
-
DQS falling edge to CK setup time
tDSS
0.3
-
22
Min
Max
21
-
24
-
14
100K
7
-
3
-
4
-
2
-
7
-
4
-
2
-
11
-
2.2
6
-
-
0.45
0.55
0.45
0.55
-0.45
0.45
-0.45
0.45
-
0.35
tHPmin
-tQHS
-
tCH/L
min
-
-
0.35
0.75
-
0.75
-
0.4
0.6
0.4
0.6
0.85
1.15
0.35
-
0.35
-
0.3
-
25
Min
Max
Unit Note
18
-
CK
21
-
CK
12
100K CK
6
-
CK
3
-
CK
4
-
CK
1
-
CK
6
-
CK
3
-
CK
2
-
CK
9
-
CK
2.5
6
ns
-
-
ns
0.45
0.55 CK
0.45
0.55 CK
-0.6
0.6
ns
-0.6
0.6
ns
-
0.35 ns
tHPmin
-tQHS
-
ns 1,6
tCH/L
min
-
ns 1,5
-
0.35 ns 6
0.75
-
ns 2
0.75
-
ns 2
0.4
0.6 CK
0.4
0.6 CK
0.85
1.15 CK
0.35
-
ns 3
0.35
-
ns 3
0.3
-
CK
Rev. 0.7 / Jun. 2004
25