HY5DV281622DT Datasheet, PDF (27/31 Pages) Hynix Semiconductor – 128M(8Mx16) GDDR SDRAM

HY5DV281622DT
AC CHARACTERISTICS - I (AC operating conditions unless otherwise noted)
Parameter
33
Symbol
Min Max
36
Min Max
4
Min Max
5
Min Max
6
Min Max
Unit Note
Row Cycle Time
tRC
18
-
16
-
15
-
12
-
11
- CK
Auto Refresh Row Cycle Time tRFC
22
-
20
-
18
-
14
-
12
- CK
Row Active Time
tRAS
12 100K 11 100K 10 100K 8 100K 7 100K CK
Row Address to Column Address ^tRCDRD
6
-
5
-
5
-
4
-
4
- CK
Delay
tRCDWT
2
-
2
-
2
-
2
-
2
- CK
Row Active to Row Active Delay tRRD
2
-
2
-
2
-
2
-
2
- CK
Column Address to Column
Address Delay
tCCD
1
-
1
-
1
-
1
-
1
- CK
Row Precharge Time
tRP
6
-
5
-
5
-
4
-
4
- CK
Last Data-In to Precharge Delay
(Write Recovery Time : tWR)
tDPL
3
-
3
-
3
-
3
-
2
- CK
Last Data-In to Read Command tDRL
2
-
2
-
2
-
2
-
2
- CK
Auto Precharge Write Recovery +
Precharge Time
tDAL
9
-
8
-
8
-
7
-
6
- CK
System Clock Cycle
Time
CL = 4.0
tCK
CL = 3.0
3.3 6.0 3.6 6.0 4.0 6.0
-
-
-
- ns
-
-
-
-
4.3 7.0 5.0 7.0 6.0 7.0 ns
Clock High Level Width
tCH
0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 CK
Clock Low Level Width
tCL
0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 CK
Data-Out edge to Clock edge
Skew
tAC
-0.7 0.7 -0.7 0.7 -0.7 0.7 -0.7 0.7 -0.75 0.75 ns
DQS-Out edge to Clock edge
Skew
tDQSCK -0.7 0.7 -0.7 0.7 -0.7 0.7 -0.7 0.7 -0.75 0.75 ns
DQS-Out edge to Data-Out edge
Skew
tDQSQ
-
0.4
-
0.4
-
0.4
- 0.45 -
0.5 ns
Data-Out hold time from DQS tQH
tHPmin
-tQHS
-
tHPmin
-tQHS
-
tHPmin
-tQHS
-
tHPmin
-tQHS
-
tHPmin
-tQHS
-
ns 1, 6
Clock Half Period
tHP
tCH/L
min
-
tCH/L
min
-
tCH/L
min
-
tCH/L
min
-
tCH/L
min
-
ns 1, 5
Data Hold Skew Factor
tQHS
-
0.4
-
0.4
-
0.4
- 0.75 - 0.75 ns 6
Input Setup Time
tIS
0.9
-
0.9
-
0.9
-
0.9
-
0.9
- ns 2
Input Hold Time
tIH
0.9
-
0.9
-
0.9
-
0.9
-
0.9
- ns 2
Rev. 0.5 / Aug. 2003
27