HY27UG088G5M Datasheet, PDF (24/50 Pages) Hynix Semiconductor – 8Gbit (1Gx8bit) NAND Flash

HY27UG088G(5/D)M Series
8Gbit (1Gx8bit) NAND Flash
Parameter
Symbol
Min
CLE Setup time
tCLS
15
CLE Hold time
tCLH
5
CE setup time
tCS
25
CE hold time
tCH
5
WE pulse width
tWP
15
ALE setup time
tALS
15
ALE hold time
tALH
5
Data setup time
tDS
15
Data hold time
tDH
5
Write Cycle time
tWC
30
WE High hold time
tWH
10
Address to Data Loading Time
tADL⁽²⁾
100
Data Transfer from Cell to register
tR
ALE to RE Delay
tAR
15
CLE to RE Delay
tCLR
15
Ready to RE Low
tRR
20
RE Pulse Width
tRP
15
WE High to Busy
tWB
Read Cycle Time
tRC
30
RE Access Time
tREA
RE High to Output High Z
tRHZ
CE High to Output High Z
tCHZ
Cache read RE High
tCRRH
100
RE High to Output Hold
tRHOH
15
RE Low to Output Hold
tRLOH
5
CE High to Output Hold
tCOH
15
RE High Hold Time
tREH
10
Output High Z to RE low
tIR
0
CE Access Time
tCEA
WE High to RE low
tWHR
60
Device Resetting Time
(Read / Program / Copy-Back Program / Erase)
tRST
Write Protection time
tWW⁽³⁾
100
Table 12: AC Timing Characteristics
3.3Volt
Max
25
100
25
50
50
30
5/10/40/500⁽¹⁾
NOTE:
1. If Reset Command (FFh) is written at Ready state, the device goes into Busy for maximum 5us
2. tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle.
3. Program / Erase Enable Operation : WP high to WE High.
Program / Erase Disable Operation : WP Low to WE High.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
ns
Rev. 0.6 / Dec. 2006
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