HY27UG088G5M Datasheet, PDF (14/50 Pages) Hynix Semiconductor – 8Gbit (1Gx8bit) NAND Flash

HY27UG088G(5/D)M Series
8Gbit (1Gx8bit) NAND Flash
3.3 Block Erase.
The Erase operation is done on a block basis. Block address loading is accomplished in three cycles initiated by an
Erase Setup command (60h). Only address A18 to A29 (X8) is valid while A12 to A17 (X8) is ignored. The Erase Con-
firm command (D0h) following the block address loading initiates the internal erasing process. This two-step sequence
of setup followed by execution command ensures that memory contents are not accidentally erased due to external
noise conditions. At the rising edge of WE after the erase confirm command input, the internal write controller handles
erase and erase-verify. Once the erase process starts, the Read Status Register command may be entered to read the
status register. The system controller can detect the completion of an erase by monitoring the R/B output, or the Sta-
tus bit (I/O 6) of the Status Register. Only the Read Status command and Reset command are valid while erasing is in
progress. When the erase operation is completed, the Write Status Bit (I/O 0) may be checked.
Figure 19 details the sequence.
Rev. 0.6 / Dec. 2006
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