HY5DU573222F Datasheet, PDF (22/30 Pages) Hynix Semiconductor – 256M(8Mx32) GDDR SDRAM

1HY5DU573222F(P)
DC CHARACTERISTICS II (TA=0 to 70^oC, Voltage referenced to VSS = 0V)
Parameter
Sym
bol
Test Condition
Speed
Unit Note
2 22 25 28 33 36 4 5
Operating Current
One bank; Active - Precharge;
tRC=tRC(min); tCK=tCK(min);
IDD0
DQ,DM and DQS inputs
changing twice per clock cycle;
350 330 310 290 270 260 250 250 mA
1
address and control inputs
changing once per clock cycle
Operating Current
IDD1
Burst length=2, One bank active
tRC ≥ tRC(min), IOL=0mA
390 370 350 330 310 300 290 280 mA
1
Precharge Standby
Current in Power
Down Mode
IDD2P CKE ≤ VIL(max), tCK=min
50 50 50 50 50 50 50 50 mA
Precharge Standby
Current in Non
Power Down Mode
CKE ≥ VIH(min), /CS ≥ VIH(min),
IDD2N tCK = min, Input signals are
270 260 250 230 210 210 210 200 mA
changed one time during 2clks
Active Standby Cur-
rent in Power Down
Mode
IDD3P CKE ≤ VIL(max), tCK=min
70 70 70 60 50 50 50 50 mA
Active Standby Cur-
CKE ≥ VIH(min), /CS ≥ VIH(min),
rent in Non Power IDD3N tCK=min, Input signals are
340 320 300 280 270 260 250 240 mA
Down Mode
changed one time during 2clks
Burst Mode Operat-
ing Current
IDD4
tCK ≥ tCK(min), IOL=0mA
All banks active
850 800 750 700 600 550 550 550 mA 1
Auto Refresh Current
IDD5
tRC ≥ tRFC(min),
All banks active
600 600 600 600 500 500 500 500 mA 1,2
Self Refresh Current IDD6 ^{CKE ≤ 0.2V}
8 8 8 8 8 8 8 8 mA
Operating Current -
Four Bank Operation
Four bank interleaving with
IDD7 BL=4, Refer to the following
page for detailed test condition
1100 1000 900
800
700
600
600
600
mA
Note :
1. IDD1, IDD4 and IDD5 depend on output loading and cycle rates. Specified values are measured with the output open.
2. Min. of tRFC (Auto Refresh Row Cycle Time) is shown at AC CHARACTERISTICS.
Rev. 1.1 / May. 2005
22