HY5DU573222F Datasheet, PDF (2/30 Pages) Hynix Semiconductor – 256M(8Mx32) GDDR SDRAM

1HY5DU573222F(P)
Revision History
No.
History
0.1 1) Defined Target Spec.
0.2 1) Supports Lead free parts for each speed grade
0.3 1) CL, tCK_max, tRAS, tDAL change & Comment of DLL_off condition
0.4
1) Changed Cas Latency to 4 clock from 5 clock at 300Mhz/275Mhz/
250Mhz speed bin
0.5
1) Changed IDD & 500Mhz speed bin insert,
2) Changed tRCDWR, tWR at 450Mhz speed bin
1.0 Changed Cas Latency to 4 clock from 5 clock at 350MHz speed bin
1.1 Added 200Mhz Speed Bin
Draft Date
Aug. 2003
Feb. 2004
Jun. 2004
Sep. 2004
Remark
Oct. 2004
Feb. 2005
May. 2005
Rev. 1.1 / May. 2005
2