HY62V8400A Datasheet, PDF (2/11 Pages) Hynix Semiconductor – 512K x8 bit 3.3V Low Power CMOS slow SRAM

HY62V8400A Series
DESCRIPTION
FEATURES
The HY62V8400A is a high-speed, low power and
4M bits CMOS SRAM organized as 512K words
by 8 bits. The HY62V8400A uses Hynix's high
performance twin tub CMOS process technology
and was designed for high-speed and low power
circuit technology. It is particularly well suited for
use in high-density and low power system
applications. This device has a data retention
mode that guarantees data to remain valid at the
minimum power supply voltage of 2.0V.
• Fully static operation and Tri-state outputs
• TTL compatible inputs and outputs
• Low power consumption
• Battery backup(LL-part)
-. 2.0V(min) data retention
• Standard pin configuration
-. 32pin 525mil SOP
-. 32pin 400mil TSOP-II
(Standard and Reversed)
Product
Voltage Speed
No.
(V)
(ns)
HY62V8400A 3.0~3.6 70/85/100
HY62V8400A-E 3.0~3.6 70/85/100
HY62V8400A-I 3.0~3.6 70/85/100
Note 1. Current value is max.
Operation
Current/Icc(mA)
5
5
5
Standby Current(uA)
LL
20
30
30
Temperature
(°C)
0~70
-25~70
-40~70
PIN CONNECTION
A18
A16
1
2
A14 3
A12 4
A7 5
A6 6
A5 7
A4 8
A3 9
A2 10
A1 11
A0 12
I/O1 13
I/O2 14
I/O3 15
Vss 16
32
31
30
Vcc A18
A15 A16
A17 A14
1
2
3
29 /WE A12 4
28 A13
A7 5
27 A8
A6 6
26 A9
A5 7
25
24
23
22
21
20
A11
A4
/OE
A3
A10
A2
/CS
A1
I/O8
A0
I/O7 I/O1
8
9
10
11
12
13
19
18
17
I/O6 I/O2
I/O5 I/O3
I/O4 Vss
14
15
16
32
31
Vcc
A15
Vcc
A15
32
31
30 A17 A17 30
29 /WE /WE 29
28 A13 A13 28
27 A8
A8 27
26 A9
A9 26
25 A11 A11 25
24 /OE /OE 24
23 A10 A10 23
22 /CS /CS 22
21 I/O8 I/O8 21
20 I/O7 I/O7 20
19
18
I/O6 I/O6
I/O5 I/O5
19
18
17 I/O4 I/O4 17
1
2
3
4
5
A18
A16
A14
A12
A7
6
7
A6
A5
8
A4
9
10
A3
A2
11
12
A1
A0
13 I/O1
14 I/O2
15 I/O3
16 Vss
SOP
TSOP-II(Standard)
TSOP-II(Reversed)
PIN DESCRIPTION
Pin Name
/CS
/WE
/OE
A0 ~ A18
I/O1 ~ I/O8
Vcc
Vss
Pin Function
Chip Select
Write Enable
Output Enable
Address Input
Data Input/Output
Power(3.0~3.6V)
Ground
BLOCK DIAGRAM
A0
ROW DECODER
I/O1
MEMORY ARRAY
512Kx 8
I/O8
A18
/CS
/OE
/WE
Rev 06 / Apr. 2001
2