HY628100B Datasheet, PDF (2/10 Pages) Hynix Semiconductor – 128K x8 bit 5.0V Low Power CMOS slow SRAM

HY628100B Series
DESCRIPTION
FEATURES
The HY628100B is a high speed, low power and
1M bit CMOS Static Random Access Memory
organized as 131,072 words by 8bit. The
HY628100B uses high performance CMOS
process technology and designed for high speed
low power circuit technology. It is particulary well
suited for used in high density low power system
application. This device has a data retention
mode that guarantees data to remain valid at a
minimum power supply voltage of 2.0V.
• Fully static operation and Tri-state output
• TTL compatible inputs and outputs
• Battery backup(L/LL-part)
-. 2.0V(min) data retention
• Standard pin configuration
-. 32pin SOP - 525mil
-. 32pin TSOPI - 8X20(Standard)
Product
Voltage
Speed
Operation
No
(V)
(ns)
Current/Icc(mA)
HY628100B 4.5~5.5 50*/55/70/85
10
HY628100B-E 4.5~5.5 50*/55/70/85
10
HY628100B-I 4.5~5.5 50*/55/70/85
10
Comment : 50ns is available with 30pF test load.
Standby Current(uA)
L
LL
100
20
100
30
100
30
Temperature
(°C)
0~70
-25~85
-40~85
PIN CONNECTION
NC 1
32
A16 2
31
A14 3
30
A12 4
29
A7 5
28
A6 6
27
A5 7
26
A4 8
25
A3 9
24
A2 10
23
A1 11
22
A0 12
21
I/O1 13
20
I/O2 14
19
I/O3 15
18
Vss 16
17
SOP
Vcc
A15
CS2
/WE
A13
A8
A9
A11
/OE
A10
/CS1
I/O8
I/O7
I/O6
I/O5
I/O4
A11 1
A9 2
A8 3
A13 4
/WE 5
CS2 6
A15 7
Vcc 8
NC 9
A16 10
A14 11
A12 12
A7 13
A6 14
A5 15
A4 16
32 /OE
31 A10
30 /CS1
29 DQ8
28 DQ7
27 DQ6
26 DQ5
25 DQ4
24 Vss
23 DQ3
22 DQ2
21 DQ1
20 A0
19 A1
18 A2
17 A3
TSOP-I(Standard)
PIN DESCRIPTION
BLOCK DIAGRAM
A0
Pin Name
Pin Function
/CS1
Chip Select 1
CS2
Chip Select 2
/WE
Write Enable
/OE
Output Enable
A0 ~ A16
Address Inputs
I/O1 ~ I/O8
Data Inputs / Outputs
Vcc
Power(4.5V~5.5V)
A16
Vss
Ground
/CS1
CS2
/OE
/WE
ROW
DECODER
MEMORY ARRAY
128K x 8
I/O1
I/O8
Rev 12 / Apr.2001
2