HYMP112S64MP8 Datasheet, PDF (16/17 Pages) Hynix Semiconductor – DDR2 SDRAM SO-DIMM

SERIAL PRESENCE DETECT
Byte#
Function Description
0 Number of bytes utilized by module manufacturer
1 Total number of Bytes in SPD device
2 Fundamental memory type
3 Number of row address on this assembly
4 Number of column address on this assembly
5 Number of DIMM ranks
6 Module data width
7 Module data width (continued)
8 Voltage Interface level of this assembly
9 DDR SDRAM cycle time at CL=5
10 DDR SDRAM access time from clock (tAC)
11 DIMM Configuration type
12 Refresh Rate and Type
13 Primary DDR SDRAM width
14 Error Checking DDR SDRAM data width
15 Reserved
16 Burst Lengths Supported
17 Number of banks on each SDRAM Device
18 CAS latency supported
19 Reserved
20 DIMM Type
21 DDR SDRAM module attributes
22 DDR SDRAM device attributes : General
23 DDR SDRAM cycle time at CL=4(tCK)
24 DDR SDRAM access time from clock at CL=4(tAC)
25 DDR SDRAM cycle time at CL=3(tCK)
26 DDR SDRAM access time from clock at CL=3(tAC)
27 Minimum Row Precharge Time(tRP)
28 Minimum Row Activate to Row Active delay(tRRD)
29 Minimum RAS to CAS delay(tRCD)
30 Minimum active to precharge time(tRAS)
31 Module rank density
32 Address and command input setup time before clock (tIS)
33 Address and command input hold time after clock (tIH)
34 Data input setup time before clock (tDS)
35 Data input hold time after clock (tDH)
36 Write recovery time(tWR)
37 Internal write to read command delay(tWTR)
38 Internal read to precharge command delay(tRTP)
39 Memory analysis probe characteristics
40 Extension of byte 41 tRC and byte 42 tRFC
41 Minimum active / auto-refresh time ( tRC)
Rev. 0.1/ July 2004
HYMP112S64(L)MP8
Bin Sort : E3(DDR2 400 3-3-3), E4(DDR2 400 4-4-4),
C4(DDR2 533 4-4-4), C5(DDR2 533 5-5-5)
Speed
Grade
all
all
all
all
all
all
all
all
all
E3,E4
C4,C5
E3,E4
C4,C5
all
all
all
all
all
all
all
all
all
all
E3,E4,C5
C4
E3,E4,C5
C4
E3,C4
E4,C5
E3,C4
E4,C5
E3, C4
E4
C5
all
E3, C4
E4
C5
E3
E4,C4,C5
all
E3, E4
C4, C5
E3, E4
C4, C5
E3, E4
C4, C5
E3, E4
C4, C5
all
E3, E4
C4, C5
all
E3,E4,C4
C5
E3
C4
E4
C5
Function
Supported
128 Bytes
256 Bytes
DDR2 SDRAM
14
10
30.0mm/stack/2rank
64 Bits
-
SSTL 1.8V
5.0 ns
3.75 ns
+/-0.6ns
+/-0.5ns
non-ECC
7.8us & Self refresh
x8
None
-
4,8
4
3, 4, 5
-
SO-DIMM
Normal
-
5.0ns
3.75ns
+/-0.6ns
+/-0.5ns
5.0ns
Undefined
+/-0.6ns
Undefined
15ns
20ns
18.75ns
7.5ns
15ns
20ns
18.75ns
40ns
45ns
512MB
0.6ns
0.5ns
0.6ns
0.5ns
0.40ns
0.35ns
0.40ns
0.35ns
15ns
10ns
7.5ns
7.5ns
Undefined
Undefined
tRC extended
55ns
60ns
65ns
63.75ns
Hexa
Value
80
08
08
0E
0A
71
40
00
05
50
3D
60
50
00
82
08
00
00
0C
04
38
00
04
00
00
50
3D
60
50
50
00
60
00
3C
50
4B
1E
3C
50
4B
28
2D
80
60
50
60
50
40
35
40
35
3C
28
1E
1E
00
00
50
37
3C
41
3F
Note
1
1
2
2
2
2
2
2
16