HMP31GP7AFR4C-Y5 Datasheet, PDF (16/18 Pages) Hynix Semiconductor – 240pin Registered DDR2 SDRAM DIMMs based on 2Gb version A

1240pin Registered DDR2 SDRAM DIMMs
Parameter
Exit self refresh to a non-read command
Exit self refresh to a read command
Exit precharge power down to any non-read
command
Exit active power down to read command
Exit active power down to read command
(Slow exit, Lower power)
CKE minimum pulse width
(high and low pulse width)
ODT turn-on delay
ODT turn-on
ODT turn-on(Power-Down mode)
ODT turn-off delay
ODT turn-off
ODT turn-off (Power-Down mode)
ODT to power down entry latency
ODT power down exit latency
OCD drive mode output delay
Minimum time clocks remains ON after CKE
asynchronously drops LOW
Average periodic Refresh Interval
Symbol
tXSNR
tXSRD
tXP
tXARD
tXARDS
tCKE
tAOND
tAON
tAONPD
tAOFD
tAOF
tAOFPD
tANPD
tAXPD
tOIT
tDelay
tREFI
tREFI
DDR2-667
min
max
tRFC + 10
200
-
2
-
2
7 - AL
DDR2-800
min
max
tRFC + 10
200
-
2
-
2
8 - AL
Unit Note
ns
tCK
tCK
tCK
tCK
3
3
tCK
2
2
2
2
tCK
tAC(min)
tAC(max)
+0.7
tAC(min)
tAC(max)
+0.7
ns
tAC(min)+2
2tCK+
tAC(max)+1
tAC(min)
+2
2tCK+
tAC(max)+1
ns
2.5
2.5
2.5
2.5
tCK
tAC(min)
tAC(max)+ 0.6 tAC(min)
tAC(max)
+0.6
ns
tAC(min)
+2
2.5tCK+
tAC(max)+1
tAC(min)
+2
2.5tCK+
tAC(max)+1
ns
3
3
tCK
8
8
tCK
0
12
0
12
ns
tIS+tCK+tIH
tIS+tCK
+tIH
ns
-
7.8
-
7.8
us
2
-
3.9
-
3.9
us
3
Note:
1. For details and notes, please refer to the relevant HYNIX component datasheet H5PS2G[4,8]3AFR.
2. 0°C †
T_CASE †
°C

°C ģ
T_CASE
†
°C
Rev. 0.1 / Jan. 2009
16