HMP31GP7AFR4C-Y5 Datasheet, PDF (15/18 Pages) Hynix Semiconductor – 240pin Registered DDR2 SDRAM DIMMs based on 2Gb version A

1240pin Registered DDR2 SDRAM DIMMs
AC Timing Parameters by Speed Grade (DDR2-667 & DDR2-800)
Parameter
Symbol
DDR2-667
min
max
DDR2-800
min
max
DQ output access time from CK/CK
tAC
-450
+450
-400
+400
DQS output access time from CK/CK
tDQSCK
-400
+400
-350
+350
CK high-level width
tCH
0.45
0.55
0.45
0.55
CK low-level width
tCL
0.45
0.55
0.45
0.55
CK half period
tHP
min(tCL,
-
min(tCL,
-
tCH)
tCH)
Clock cycle time, CL=x
tCK
3000
8000
2500
DQ and DM input setup time
(differential strobe)
tDS
100
-
50
-
DQ and DM input hold time
(differential strobe)
tDH
175
-
125
-
Control & Address input pulse width for each input
tIPW
0.6
-
0.6
-
DQ and DM input pulse width for each input
tDIPW
0.35
-
0.35
-
Data-out high-impedance time from CK/CK
tHZ
-
tAC max
-
tAC max
DQS low-impedance time from CK/CK
tLZ(DQS)
tAC min
tAC max
tAC min
tAC max
DQ low-impedance time from CK/CK
tLZ(DQ)
2*tAC min
tAC max
2*tAC min
tAC max
DQS-DQ skew for DQS and associated DQ signals
tDQSQ
-
240
-
200
DQ hold skew factor
tQHS
-
340
-
300
DQ/DQS output hold time from DQS
tQH
tHP - tQHS
-
tHP - tQHS
-
First DQS latching transition to associated clock
edge
tDQSS
- 0.25
+ 0.25
- 0.25
+ 0.25
DQS input high pulse width
tDQSH
0.35
-
0.35
-
DQS input low pulse width
tDQSL
0.35
-
0.35
-
DQS falling edge to CK setup time
tDSS
0.2
-
0.2
-
DQS falling edge hold time from CK
tDSH
0.2
-
0.2
-
Mode register set command cycle time
tMRD
2
-
2
-
Write preamble
tWPRE
0.35
-
0.35
-
Write postamble
tWPST
0.4
0.6
0.4
0.6
Auto-Refresh to Active/Auto-Refresh command
period
tRFC
127.5
-
127.5
-
Row Active to Row Active Delay
for 1KB page size
tRRD
7.5
-
7.5
-
Address and control input setup time
tIS
200
-
175
-
Address and control input hold time
tIH
275
-
250
-
Read preamble
tRPRE
0.9
1.1
0.9
1.1
Read postamble
tRPST
0.4
0.6
0.4
0.6
Activate to precharge command
tRAS
45
70000
45
70000
Active to active command period for 1KB page size
products
tRRD
7.5
-
7.5
-
Row Active to Row Active Delay
for 2KB page size
tRRD
10
-
10
-
Four Active Window for 1KB page size products
tFAW
37.5
-
35
-
Four Activate Window for 2KB page size
tFAW
50
-
50
-
CAS to CAS command delay
tCCD
2
2
Write recovery time
tWR
15
-
15
-
Auto precharge write recovery + precharge time
tDAL
WR+tRP
-
WR+tRP
-
Internal write to read command delay
tWTR
7.5
-
7.5
-
Internal read to precharge command delay
tRTP
7.5
7.5
Unit Note
ps
ps
tCK
tCK
ps
ps
ps
1
ps
1
tCK
tCK
ps
ps
ps
ps
ps
ps
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
ns
ns
ps
ps
tCK
tCK
ns
ns
ns
ns
ns
tCK
ns
tCK
ns
ns
Rev. 0.1 / Jan. 2009
15