HY5S2B6DLF-SE Datasheet, PDF (14/26 Pages) Hynix Semiconductor – 4Banks x 2M x 16bits Synchronous DRAM

1HY5S2B6DLF(P)-xE
4Banks x 2M x 16bits Synchronous DRAM
URRENT STATE TRUTH TABLE (Sheet 4 of 4)
Current
State
Command
CS RAS CAS WE
BA0/
BA1
A11-A0
Description
Action
Notes
Write
Recovering
H
X
X
X
X
X
Device Deselect
No Operation:
Row Active after tDPL
LL L L
OP CODE
Mode Register Set ILLEGAL
13,14
LL L H X
X
Auto or Self Refresh ILLEGAL
13
L L H L BA
X
Precharge
Write
L L H H BA
Row Add. Bank Activate
Recovering
with Auto ^{L H L L BA Col Add. A10 Write/WriteAP}
Precharge _{L H L H BA Col Add. A10 Read/ReadAP}
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
4,13
4,12
4,12
4,9,12
LHH H X
X
No Operation
No Operation:
Precharge after tDPL
HX X X
X
X
Device Deselect
No Operation:
Precharge after tDPL
LL L L
OP CODE
Mode Register Set ILLEGAL
13,14
LL L H X
X
Auto or Self Refresh ILLEGAL
13
L L H L BA
X
Precharge
ILLEGAL
13
L L H H BA
Row Add. Bank Activate
ILLEGAL
13
Refreshing ^{L H L L BA Col Add. A10 Write/WriteAP}
ILLEGAL
13
L H L H BA Col Add. A10 Read/ReadAP
ILLEGAL
13
LHH H X
X
No Operation
No Operation:
idle after tRC
HX X X
X
X
Device Deselect
No Operation:
idle after tRC
LL L L
OP CODE
Mode Register Set ILLEGAL
13,14
LL L H X
X
Auto or Self Refresh ILLEGAL
13
L L H L BA
X
Precharge
ILLEGAL
13
L L H H BA
Row Add. Bank Activate
ILLEGAL
13
Mode
Register ^{L H L L BA Col Add. A10 Write/WriteAP}
ILLEGAL
13
Accessing _{L H L H BA Col Add. A10 Read/ReadAP}
ILLEGAL
13
LHH H X
X
No Operation
No Operation:
idle after 2 clock cycles
HX X X
X
X
Device Deselect
No Operation:
idle after 2 clock cycles
Rev. 0.3 / Feb. 2005
14