HY5S2B6DLF-SE Datasheet, PDF (13/26 Pages) Hynix Semiconductor – 4Banks x 2M x 16bits Synchronous DRAM

1HY5S2B6DLF(P)-xE
4Banks x 2M x 16bits Synchronous DRAM
CURRENT STATE TRUTH TABLE (Sheet 3 of 4)
Current
State
Command
CS RAS CAS WE
BA0/
BA1
A11-A0
Description
Action
LL L L
OP CODE
Mode Register Set ILLEGAL
LL L H X
X
Auto or Self Refresh ILLEGAL
L L H L BA
X
Precharge
No Operation:
Bank(s) idle after tRP
L L H H BA
Row Add. Bank Activate
Precharging _{L H L L BA Col Add. A10 Write/WriteAP}
ILLEGAL
ILLEGAL
L H L H BA Col Add. A10 Read/ReadAP
ILLEGAL
LHH H X
X
No Operation
No Operation:
Bank(s) idle after tRP
HX X X
X
X
Device Deselect
No Operation:
Bank(s) idle after tRP
LL L L
OP CODE
Mode Register Set ILLEGAL
LL L H X
X
Auto or Self Refresh ILLEGAL
L L H L BA
X
Precharge
ILLEGAL
LLHH
Row
Activating ^{L H L L}
LH L H
LHH H
HX X X
LL L L
LL L H
LLH L
LLHH
Write
Recovering _{L H L L}
LH L H
LHH H
BA
Row Add. Bank Activate
ILLEGAL
BA Col Add. A10 Write/WriteAP
ILLEGAL
BA Col Add. A10 Read/ReadAP
ILLEGAL
X
X
No Operation
No Operation: Row
Active after tRCD
X
X
Device Deselect
No Operation: Row
Active after tRCD
OP CODE
Mode Register Set ILLEGAL
X
X
Auto or Self Refresh ILLEGAL
BA
X
Precharge
ILLEGAL
BA
Row Add. Bank Activate
ILLEGAL
BA Col Add. A10 Write/WriteAP
Start Write:
Optional AP(A10=H)
BA Col Add. A10 Read/ReadAP
Start Read: Optional
AP(A10=H)
X
X
No Operation
No Operation:
Row Active after tDPL
Notes
13,14
13
4,12
4,12
4,12
13,14
13
4,12
4,11,1
2
4,12
4,12
13,14
13
4,13
4,12
9
Rev. 0.3 / Feb. 2005
13