HYMD512M646BFS8-J Datasheet, PDF (13/19 Pages) Hynix Semiconductor – Unbuffered DDR SO-DIMM

HYMD512M646B(L)FS8-J/M/K/H/L
AC CHARACTERISTICS - II (AC operating conditions unless otherwise noted)
- continued -
Parameter
Symbol
Write DQS Low Level Width
tDQSL
Clock to First Rising edge of DQS-In
tDQSS
Data-In Setup Time to DQS-In (DQ & DM)
tDS
Data-in Hold Time to DQS-In (DQ & DM)
tDH
DQ & DM Input Pulse Width
tDIPW
Read DQS Preamble Time
tRPRE
Read DQS Postamble Time
tRPST
Write DQS Preamble Setup Time
tWPRES
Write DQS Preamble Hold Time
tWPREH
Write DQS Postamble Time
tWPST
Mode Register Set Delay
tMRD
Exit Self Refresh to Any Execute Command tXSC
Average Periodic Refresh Interval
tREFI
DDR266A
Min Max
0.35
-
0.75 1.25
0.45
-
0.45
-
1.75
-
0.9
1.1
0.4
0.6
0
-
0.25
-
0.4
0.6
2
-
200
-
-
7.8
DDR266B
Min Max
0.35
-
0.75 1.25
0.45
-
0.45
-
1.75
-
0.9
1.1
0.4
0.6
0
-
0.25
-
0.4
0.6
2
-
200
-
-
7.8
DDR200
Min Max
0.35
-
0.72 1.28
0.5
-
0.5
-
1.75
-
0.9
1.1
0.4
0.6
0
-
0.25
-
0.4
0.6
2
-
200
-
-
7.8
Unit Note
CK
CK
ns
6,7,
ns ^11~13
ns
CK
CK
CK
CK
CK
CK
CK
8
us
Note :
1. This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter.
2. Data sampled at the rising edges of the clock : A0~A12, BA0~BA1, CKE, /CS, /RAS, /CAS, /WE.
3. For command/address input slew rate >=1.0V/ns
4. For command/address input slew rate >=0.5V/ns and <1.0V/ns
This derating table is used to increase tIS/tIH in case where the input slew-rate is below 0.5V/ns.
Input Setup / Hold Slew-rate Derating Table.
Input Setup / Hold Slew-rate
Delta tIS
Delta tIH
V/ns
ps
ps
0.5
0
0
0.4
+50
0
0.3
+100
0
5. CK, /CK slew rates are >=1.0V/ns
6. These parameters quarantee device timing, but they are not necessarily tested on each device, and they may be quaranteed by
design or tester correlation.
7. Data latched at both rising and falling edges of Data Strobes(LDQS/UDQS) : DQ, LDM/UDM.
8. Minimum of 200 cycles of stable input clocks after Self Refresh Exit command, where CKE is held high, is required to complete
Self Refresh Exit and lock the internal DLL circuit of DDR SDRAM.
9. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device
(i.e. this value can be greater than the minimum specification limits for tCL and tCH).
Rev. 0.1 / Jan. 2004
13