HYMD232G726D8-K Datasheet, PDF (11/30 Pages) Hynix Semiconductor – 184pin Registered DDR SDRAM DIMMs

184pin Registered DDR SDRAM DIMMs
IDD SPECIFICATION AND CONDITIONS (TA=0 to 70^oC, Voltage referenced to VSS = 0V)
512MB, 64Mb x 72 ECC Registered DIMM : HYMD264G726D[P]4[M]
Symbol
Test Condition
IDD0
IDD1
IDD2P
IDD2F
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
IDD6
IDD7
One bank; Active - Precharge; tRC=tRC(min);
tCK=tCK(min); DQ,DM and DQS inputs changing twice
per clock cycle; address and control inputs changing
once per clock cycle
One bank; Active - Read - Precharge; Burst Length=2;
tRC=tRC(min); tCK=tCK(min); address and control
inputs changing once per clock cycle
All banks idle; Power down mode; CKE=Low,
tCK=tCK(min)
/CS=High, All banks idle; tCK=tCK(min); CKE= High;
address and control inputs changing once per clock
cycle. VIN=VREF for DQ, DQS and DM
One bank active ; Power down mode; CKE=Low,
tCK=tCK(min)
/CS=HIGH; CKE=HIGH; One bank; Active-Precharge;
tRC=tRAS(max); tCK=tCK(min); DQ, DM and DQS
inputs changing twice per clock cycle; Address and
other control inputs changing once per clock cycle
Burst=2; Reads; Continuous burst; One bank active;
Address and control inputs changing once per clock
cycle; tCK=tCK(min); IOUT=0mA
Burst=2; Writes; Continuous burst; One bank active;
Address and control inputs changing once per clock
cycle; tCK=tCK(min); DQ, DM and DQS inputs changing
twice per clock cycle
tRC=tRFC(min) - 8*tCK for DDR200 at 100Mhz, 10*tCK
for DDR266A & DDR266B at 133Mhz; distributed refresh
CKE=<0.2V; External clock on; tCK
=tCK(min)
Normal
Low Power
Four bank interleaving with BL=4 Refer to the following
page for detailed test condition
-K
1910
2270
830
1370
920
1370
3170
3170
2870
404
377
4610
Speed
-H
1910
2270
830
1370
920
1370
3170
3170
2870
404
377
4610
-L
1820
Unit Note
mA
2090
mA
830
mA
1190
mA
920
mA
1280
mA
2810
mA
2810
mA
2690
mA
404
mA
377
mA
4250
mA
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Rev. 1.1 /May. 2005
11