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HMP512U6FFP8C-Y5 Datasheet, PDF (10/25 Pages) Hynix Semiconductor – 240pin DDR2 SDRAM Unbuffered DIMMs based on 512 Mb F ver.
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INPUT DC LOGIC LEVEL
Parameter
Input High Voltage
Input Low Voltage
Symbol
VIH(DC)
VIL(DC)
1240pin DDR2 SDRAM Unbuffered DIMMs
Min
VREF + 0.125
-0.30
Max
VDDQ + 0.3
VREF - 0.125
Unit
Note
V
V
INPUT AC LOGIC LEVEL
Parameter
AC Input logic High
AC Input logic Low
Symbol
VIH(AC)
VIL(AC)
DDR2 400, 533
Min
Max
VREF + 0.250
-
-
VREF - 0.250
DDR2 667, 800
Min
Max
VREF + 0.200
-
-
VREF - 0.200
Unit Note
V
V
AC INPUT TEST CONDITIONS
Symbol
VREF
VSWING(MAX)
SLEW
Condition
Input reference voltage
Input signal maximum peak to peak swing
Input signal minimum slew rate
Value
0.5 * VDDQ
1.0
1.0
Units
V
V
V/ns
Notes
1
1
2, 3
Notes:
1. Input waveform timing is referenced to the input signal crossing through the VREF level applied to the device
under test.
2. The input signal minimum slew rate is to be maintained over the range from VREF to VIH(ac) min for rising edges
and the range from VREF to VIL(ac) max for falling edges as shown in the below figure.
3. AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions and
VIH(ac) to VIL(ac) on the negative transitions.
VSWING(MAX)
delta TF
delta TR
Falling Slew =
VREF - VIL(ac) max
delta TF
Rising Slew =
< Figure : AC Input Test Signal Waveform >
VDDQ
VIH(ac) min
VIH(dc) min
VREF
VIL(dc) max
VIL(ac) max
VSS
VIH(ac) min - VREF
delta TR
Rev. 0.1 / June 2008
10
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