HMP512U6FFP8C-Y5 Datasheet, PDF (1/25 Pages) Hynix Semiconductor – 240pin DDR2 SDRAM Unbuffered DIMMs based on 512 Mb F ver.

240pin DDR2 SDRAM Unbuffered DIMMs based on 512 Mb F ver.
This Hynix unbuffered Dual In-Line Memory Module(DIMM) series consists of 512Mb C ver. DDR2 SDRAMs
in Fine Ball Grid Array(FBGA) packages on a 240pin glass-epoxy substrate. This Hynix 512Mb C ver. based
DDR2 Unbuffered DIMM series provide a high performance 8 byte interface in 133.35mm width form factor
of industry standard. It is suitable for easy interchange and addition.
FEATURES
• JEDEC standard Double Data Rate2 Synchro-
nous DRAMs (DDR2 SDRAMs) with 1.8V +/-
0.1V Power Supply
• All inputs and outputs are compatible with
SSTL_1.8 interface
• 4 Bank architecture
• Posted CAS
• Programmable CAS Latency 3 , 4 , 5, 6
• OCD (Off-Chip Driver Impedance Adjustment)
• ODT (On-Die Termination)
• Fully differential clock operations (CK & CK)
• Programmable Burst Length 4 / 8 with both
sequential and interleave mode
• Auto refresh and self refresh supported
• Partial Array Self Refresh supported
• 8192 refresh cycles / 64ms
• Serial presence detect with EEPROM
• DDR2 SDRAM Package: 60ball FBGA(64Mx8)
• 133.35 x 30.00 mm form factor
• Lead-free Products are RoHS compliant
ORDERING INFORMATION
Part Name
HMP512U6FFP8C-Y5/S5/S6
HMP564U7FFP8C-Y5/S5/S6
HMP512U7FFP8C-Y5/S5/S6
Density
Organization
# of # of
DRAMs ranks
Materials
ECC
1GB
128Mx64
16
2 Lead free None
512MB
64Mx72
9
1 Lead free ECC
1GB
128Mx72
18
2 Lead free ECC
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.1 / Jun 2008
1