GMS90C320 Datasheet, PDF (10/46 Pages) Hynix Semiconductor – HYNIX SEMICONDUCTOR INC. 8-BIT SINGLE-CHIP MICROCONTROLLERS

GMS90C320
Pin Definitions and functions
Symbol
P1.0-P1.7
P3.0-P3.7
XTAL2
XTAL1
Pin Number
P-LCC-44
P-DIP-40
P-MQFP-
44
2-9
1-8 40-44,
1-3
2
3
11,13-
19
1
2
10-17
40
41
5, 7-
13
11
10
5
13
11
7
14
12
8
15
13
9
16
14
10
17
15
11
18
16
12
19
17
13
20
18
14
21
19
15
Input/
Output
I/O
I/O
O
I
Function
Port1
is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins
that have 1s written to them are pulled high by the internal pull-up
resistors and can be used as inputs. As inputs, port 1 pins that are
externally pulled low will source current because of the pulls-ups
(I_IL, in the DC characteristics). Pins P1.0 and P1.1 also. Port 1
also receives the low-order address byte during program memory
verification. Port1 also serves alternate functions of Timer 2.
P1.0/T2: Timer/counter 2 external count input
P1.1/T2EX: Timer/counter 2 trigger input
Port 3
is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins
that have 1s written to them are pulled high by the internal pull-up
resistors, and in that state they can be used as inputs. As inputs,
port 3 pins being externally pulled low will source current (I_IL, in
the DC characteristics) because of internal pulls-up resistors. Port
3 also serves the special features of the 80C51 family, as listed
below.
P3.0/RxD
receiver data input (asynchronous) or data input
output (synchronous) of the serial interface 0
P3.1 / TxD transmitter data output (asynchronous) or clock
output (synchronous) of the serial interface 0
P3.2 / INT0 interrupt 0 input / timer 0 gate control
P3.3 / INT1 interrupt 1 input / timer 1 gate control
P3.4 / T0 counter 0 input
P3.5 / T1 counter 1 input
P3.6 / WR the write control signal latches the data byte from
port 0 into the external data memory
P3.7 / RD
the read control signal enables the external data
memory to port 0
XTAL2
Output of the inverting oscillator amplifier
XTAL1
Input to the inverting oscillator amplifier and input to the internal
clock generator circuits.
To drive the device from an external clock source, XTAL1 should
be driven, while XTAL2 is left unconnected. There are no require-
ments on the duty cycle of the external clock signal, since the
input to the internal clocking circuitry is divided down by a divide-
by-two flip-flop. Minimum and maximum high and low times as
well as rise fall times specified in the AC characteristics must be
observed.
6
OCT. 2000 Ver 1.2