HCPL-7100 Datasheet, PDF (9/14 Pages) Agilent(Hewlett-Packard) – High Speed CMOS Optocouplers

Notes:
1. The LED is OFF when the V_I is high and ON when V_I is low.
2. Device considered a two terminal device; pins 1-4 shorted together and pins 5-8 shorted together.
3. In accordance with UL 1577, for devices with minimum V_ISO specified at 3750 V rms, each optocoupler is proof-tested by applying an
insulation test voltage greater than 4500 V rms for one second (leakage current detection limit I_I-O < 5 µA). This test is performed
before the method b, 100% production test for partial discharge shown in the VDE 0884 Insulation Characteristics Table.
4. C_I is the capacitance measured at pin 2 (V_I).
5. t_PHL propagation delay is measured from the 50% level on the falling edge of the V_I signal to the logic switching level of the V_O signal.
t_PLH propagation delay is measured from the 50% level on the rising edge of the V_I signal to the logic switching level of the V_O signal.
6. The logic switching levels are 1.5 V for TTL signals (0-3 V) and 2.5 V for CMOS signals (0-5 V).
7. PWD is defined as |t_PHL - t_PLH|. %PWD (percent pulse width distortion) is equal to PWD in ns divided by symbol duration (bit length)
in ns.
8. Minimum data rate is calculated as follows: %PWD/PWD where %PWD is typically chosen by the design engineer (30% is common).
9. t_PSK is equal to the worst case difference in t_PHL and/or t_PLH that will be seen between units at the same temperature, supply voltage,
and output load within the recommended operating condition range.
10. CM_H is the maximum common mode voltage slew rate that can be sustained while maintaining V_O > 3.2 V. CM_L is the maximum
common mode voltage slew rate that can be sustained while maintaining V_O < 0.8 V. The common mode voltage slew rates apply to
both rising and falling common mode voltage edges.
11. Unloaded dynamic power dissipation is calculated as follows: C_PD • V_DD2 • f + I_DD • V_DD where f is switching frequency in MHz.
Figure 1. Recommended Application Circuit.
Figure 2. Recommended Printed Circuit Board Layout.
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