HCPL-7100 Datasheet, PDF (7/14 Pages) Agilent(Hewlett-Packard) – High Speed CMOS Optocouplers

Switching Specifications
Guaranteed across recommended operating conditions. Test conditions represent worst case values for the
parameter under test. Test conditions that are not specified can be anywhere within their operating range. All
typicals are at 25°C and 5 V supplies unless otherwise noted.
Parameter
Symbol Device Min. Typ. Max. Unit Test Conditions
Fig. Note
Propagation
Delay Time
to Logic
Low Output
Propagation
Delay Time
to Logic
High Output
t_PHL HCPL-7100
HCPL-7101
HCPL-7100
HCPL-7101
t_PLH HCPL-7100
HCPL-7101
HCPL-7100
HCPL-7101
70
ns C_L = 50 pF
CMOS Signal Levels
28 40
70
ns C_L = 15 pF
TTL Signal Levels
40
70
ns C_L = 50 pF
CMOS Signal Levels
27 40
70
ns C_L = 15 pF
TTL Signal Levels
40
7, 8 5, 6
7, 8 5, 6
Pulse Width
Distortion
|t_PHL- t_PLH|
PWD
HCPL-7100
HCPL-7101
HCPL-7100
HCPL-7101
20
ns C_L = 50 pF
CMOS Signal Levels
2
6
20
ns C_L = 15 pF
TTL Signal Levels
6
7, 9 6, 7
Data Rate
Propagation
Delay Skew
HCPL-7100 15
HCPL-7101 50 65
t_PSK
HCPL-7101
MBd % PWD < 30%
10 ns
8
10 9
Output Rise
Time
(10-90%)
t_R
HCPL-7100
12
HCPL-7101
10
Output Fall
Time
(90-10%)
t_F
HCPL-7100
8
HCPL-7101
7
Random Jitter
RJ HCPL-7101
50
ns C_L = 50 pF
7
CMOS Signal Levels
ns C_L = 50 pF
7
CMOS Signal Levels
ps rms
V₁ = 0-5 V square wave,
f = 25 MHz, input rise/
fall time = 5 ns.
R_L = 10 kΩ,
C_L = 5 pF.
TTL Threshold Levels.
Propagation
t_PZH
Delay Time From
Output Enabled
to Logic High
Output
13
ns C_L = 50 pF
12 6
CMOS Signal Levels
12
ns C_L = 15 pF
TTL Signal Levels
Propagation
t_PZL
Delay Time From
Output Enabled
to Logic Low
Output
11
ns C_L = 50 pF
12 6
CMOS Signal Levels
10
ns C_L = 15 pF
TTL Signal Levels
1-408