HDMP-1526 Datasheet, PDF (5/14 Pages) Agilent(Hewlett-Packard) – Fibre Channel Transceiver Chip

HDMP-1526 (Receiver Section)
Timing Characteristics
T_C = 0°C to +85°C, V_CC = 4.5 V to 5.25 V
Symbol
Parameter
b_sync^[1,2]
Bit Sync Time
f_lock^[2]
Frequency Lock Time
(from Time of Setting -LCKREF = 0)
f_lock_rate^[2] Frequency Lock Rate (when -LCKREF = 0)
t_{valid_before}
Time Data Valid Before Rising Edge of RBC
t_{valid_after}
Time Data Valid After Rising Edge of RBC
t_duty
t_A-B[3]
t_rxlat^[4]
RBC Duty Cycle
Rising Edge Time Difference
Receiver Latency
Units
bits
µsec
Min.
kHz/µsec
nsec
3
nsec
1.5
%
40
nsec
8.9
nsec
bits
Typ.
200
5.8
3.3
9.4
25.0
26.6
Max.
2500
500
60
9.9
33.9
36
Notes:
1. This is the recovery time for input phase jumps, per the FC-PH specification Ref 4.1, Sec 5.3.
2. Tested using C_PLL = 0.01 µF.
3. The RBC clock skew is calculated as t_A-B(max) - t_A-B(min).
4. The receiver latency, as shown in Figure 5, is defined as the time between receiving the first serial bit of a parallel data word (as
defined as the first edge of the first serial bit) and the clocking out of that parallel word (defined by the rising edge of the receive
byte clock, either RBC1 or RBC0).

,

,
,

,,
,
,,
, t-VALID BEFORE
RBC1
t-VALID AFTER
RX[0]-RX[9]
BYTSYNC
K28.5
DATA
DATA
DATA
DATA
1.4 V
2.0 V
0.8 V
2.0 V
0.8 V
RBC0
Figure 5. Receiver Section.
1.4 V

,
,
 _,
,
 ^DATABYTEC
DATA BYTE D
± DIN R5 R6 R7 R8 R9 R0 R1 R2 R3 R4 R5 R6 R7 R8 R9
t_RXLAT
RX[0]-RX[9]
DATA BYTE A
R2 R3 R4 R5
DATA BYTE D
RBC1/0
1.4 V
Figure 6. Receiver Latency.
686