HDMP-1526 Datasheet, PDF (2/14 Pages) Agilent(Hewlett-Packard) – Fibre Channel Transceiver Chip

PROTOCOL DEVICE
BYTSYNC
HDMP-1526
TRANSMITTER SECTION
PLL
PLL
RECEIVER SECTION
REFCLK
ENBYTSYNC
-LCKREF
Figure 1. Typical Application Using the HDMP-1526.
DATA BYTE
TX[0-9]
TXCAP0
TXCAP1
REFCLK
-LCKREF
RXCAP0
RXCAP1
RBC0
RBC1
DATA BYTE
RX[0-9]
FRAME
MUX
TX
PLL/CLOCK
GENERATOR
INTERNAL
Tx CLOCKS
OUTPUT
SELECT
INTERNAL
LOOPBACK
INPUT
SELECT
RX
PLL/CLOCK
RECOVERY
FRAME
DEMUX
AND
BYTE SYNC
INTERNAL
Rx CLOCKS
INPUT
SAMPLER
BYTSYNC ENBYTSYNC
Figure 2. HDMP-1526 Transceiver Block Diagram.
SERIAL DATA OUT
SERIAL DATA IN
± DOUT
LOOPEN
± DIN
HDMP-1526 Block Diagram
The HDMP-1526 was designed to
transmit and receive 10-bit wide
parallel data over a single high-
speed line, as specified for the FC-0
layer of the Fibre Channel standard.
The parallel data applied to the
transmitter is expected to be
encoded per the Fibre Channel
specification, which uses an 8B/10B
encoding scheme with special
reserve characters for link
management purposes. In order to
accomplish this task, the HDMP-
1526 incorporates the following:
• TTL Parallel I/Os
• High-Speed Phase Lock Loops
• Clock Generation/Recovery
Circuitry
• Parallel-to-Serial Converter
• High-Speed Serial Clock-and-Data
Recovery Circuitry
• Comma Character Recognition
Circuitry
• Byte Alignment Circuitry
• Serial-to-Parallel Converter
INPUT LATCH
The transmitter accepts 10-bit wide
TTL parallel data at inputs TX[0..9].
The user-provided reference clock
signal, REFCLK, is also used as the
transmit byte clock. The TX[0..9]
and REFCLK signals must be
properly aligned, as shown in
Figure 3.
TX PLL/CLOCK GENERATOR
The transmitter Phase Lock Loop
and Clock Generator (TX PLL/
CLOCK GENERATOR) block is
responsible for generating all
internal clocks needed by the
transmitter section to perform its
functions. These clocks are based on
the supplied reference byte clock
(REFCLK). REFCLK is used as both
the frequency reference clock for
the PLL and the transmit byte clock
for the incoming data latches. It is
expected to be 106.25 MHz and
properly aligned to the incoming
683