HDMP-1636 Datasheet, PDF (4/15 Pages) Agilent(Hewlett-Packard) – Gigabit Ethernet Transceiver Chip

receiver byte clocks
(RBC1/RBC0). These clocks are
180 degrees out of phase with
each other, and are alternately
used to clock the 10-bit parallel
output data.
INPUT SAMPLER
The INPUT SAMPLER is respon-
sible for converting the serial
input signal into a re-timed serial
bit stream. In order to accom-
plish this, it uses the high speed
serial clock recovered from the
RX PLL/CLOCK RECOVERY
block. This serial bit stream is
sent to the FRAME DEMUX and
BYTE SYNC block.
FRAME DEMUX AND BYTE
SYNC
The FRAME DEMUX AND BYTE
SYNC block is responsible for
restoring the 10-bit parallel data
from the high speed serial bit
stream. This block is also
responsible for recognizing the
comma character (or a K28.5
character) of positive disparity
(0011111xxx). When recognized,
the FRAME DEMUX AND BYTE
SYNC block works with the RX
PLL/CLOCK RECOVERY block to
properly align the receive byte
clocks to the parallel data. When
a comma character is detected
and realignment of the receiver
byte clocks (RBC1/RBC0) is
necessary, these clocks are
stretched, not slivered, to the
next possible correct alignment
position. These clocks will be
fully aligned by the start of the
second 2-byte ordered set. The
second comma character
received shall be aligned with the
rising edge of RBC1. Comma
characters should not be trans-
mitted in consecutive bytes to
allow the receiver byte clocks to
maintain their proper recovered
frequencies.
OUTPUT DRIVERS
The OUTPUT DRIVERS present
the 10-bit parallel recovered data
byte properly aligned to the
receive byte clocks (RBC1/RBC0),
as shown in Figure 5. These
output data buffers provide TTL
compatible signals.
HDMP-1636/46 (Transmitter Section)
Timing Characteristics
T_A = 0°C to +60°C, V_CC = 3.15 V to 3.45 V
Symbol
Parameter
t_setup
Setup Time
t_hold
t_txlat^[1]
Hold Time
Transmitter Latency
Units
nsec
nsec
nsec
bits
Min.
2
1
Typ.
TBD
TBD
Max.
Note:
1. The transmitter latency, as shown in Figure 4, is defined as the time between the latching in of the parallel data word (as triggered
by the rising edge of the transmit byte clock, REFCLK) and the transmission of the first serial bit of that parallel word (defined by
the rising edge of the first bit transmitted).
714