HDMP-1636 Datasheet, PDF (12/15 Pages) Agilent(Hewlett-Packard) – Gigabit Ethernet Transceiver Chip

TRx I/O Definition
Name
BYTSYNC
-DIN
+DIN
-DOUT
+DOUT
ENBYTSYNC
GND
GND_RXA
GND_RXHS
GND_RXTTL
GND_TXA
GND_TXHS
GND_TXTTL
LOOPEN
RBC1
RBC0
REFCLK
N/C
Pin Type
47 O-TTL
52 HS_IN
54
61 HS_OUT
62
24 I-TTL
21
S
25
58
51
S
56
S
32
S
33
46
15
S
64
S
1
S
14
19 I-TTL
30 O-TTL
31
22 I-TTL
26,27
Signal
Byte Sync Output: An active high output. Used to indicate detection of
a comma character (0011111XXX). It is only active when
ENBYTSYNC is enabled.
Serial Data Inputs: High-speed inputs. Serial data is accepted from the
± DIN inputs when LOOPEN is low.
Serial Data Outputs: High-speed outputs. These lines are active when
LOOPEN is set low. When LOOPEN is set high, these outputs are held
static at logic 1.
Enable Byte Sync Input: When high, turns on the internal byte sync
function to allow clock synchronization to a comma character,
(0011111XXX). When the line is low, the function is disabled and will
not reset registers and clocks, or strobe the BYTSYNC line.
Logic Ground: Normally 0 volts. This ground is used for internal PECL
logic. It should be isolated from the noisy TTL ground as well as possible.
Analog Ground: Normally 0 volts. Used to provide a clean ground
plane for the receiver PLL and high-speed analog cells.
Ground: Normally 0 volts.
TTL Receiver Ground: Normally 0 volts. Used for the TTL output cells
of the receiver section.
Analog Ground: Normally 0 volts. Used to provide a clean ground plane
for the PLL and high-speed analog cells.
Ground: Normally 0 volts.
TTL Transmitter Ground: Normally 0 volts. Used for the TTL input
cells of the transmitter section.
Loopback Enable Input: When set high, the high-speed serial signal is
internally wrapped from the transmitter’s serial loopback outputs back
to the receiver’s loopback inputs. Also, when in loopback mode, the
± DOUT outputs are held static at logic 1. When set low, ± DOUT outputs
and ± DIN inputs are active.
Receiver Byte Clocks: The receiver section recovers two 62.5 MHz
receive byte clocks. These two clocks are 180 degrees out of phase.
The receiver parallel data outputs are alternately clocked on the
rising edge of these clocks. The rising edge of RBC1 aligns with the
output of the comma character (for byte alignment) when detected.
Reference Clock and Transmit Byte Clock: A 125 MHz clock
supplied by the host system. The transmitter section accepts this signal
as the frequency reference clock. It is multiplied by 10 to generate the
serial bit clock and other internal clocks. The transmit side also uses this
clock as the transmit byte clock for the incoming parallel data
TX[0]..TX[9]. It also serves as the reference clock for the receive
portion of the transceiver.
These pins are factory test pins and must be left unconnected.
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