English
Language : 

HDMP-1636 Datasheet, PDF (14/15 Pages) Agilent(Hewlett-Packard) – Gigabit Ethernet Transceiver Chip
VCC*
power supply pins of the
VCC
HDMP-1636/46 as shown on the
schematic of Figure 12. All
bypass chip capacitors are
0.1 µF. The VCC_RXA and
CPLLR
VCC_TXA pins are the analog
power supply pins for the PLL
GND_TXTTL
RXCAP0
sections. The voltage into these
pins should be clean with
GND_RXTTL minimum noise. The PLL loop
filter capacitors and their pin
VCC_TXTTL
locations are also shown on
Figure 12. Notice that only two
VCC_RXTTL
VCC capacitors are required: CPLLT for
TOP VIEW
the transmitter and CPLLR for the
VCC_TXTTL
receiver. Nominal capacitance is
0.1 µF. The voltage across the
GND_TXTTL
GND_TXA
VCC_RXTTL
capacitors is on the order of 1
volt, so the capacitor can be a
low voltage type and physically
small. The PLL capacitors are
TXCAP1
placed physically close to the
appropriate pins on the HDMP-
CPLLT
GND_RXTTL
1636/46. Keeping the lines short
will prevent them from picking
up stray noise from surrounding
lines or components.
VCC*
* SUPPLY VOLTAGE INTO VCC_RXA AND VCC_TXA SHOULD
BE FROM A LOW NOISE SOURCE. ALL BYPASS CAPACITORS
AND PLL FILTER CAPACITORS ARE 0.1 µF.
Figure 12. Power Supply Bypass.
Start-up Procedure:
The transceiver start-up
procedure(s) use the following
conditions: VCC = +3.3 V ± 5%
and REFCLK = 125 MHz ± 100
ppm.
Transceiver Power
Supply Bypass and Loop
Filter Capacitors
Bypass capacitors should be
liberally used and placed as close
as possible to the appropriate
PRE-RELEASE PRODUCT
DISCLAIMER:
This product is in development at
the Hewlett-Packard CSSD in San
Jose, California. Until Hewlett-
Packard releases this product for
general sales, HP reserves the right to
alter specifications, features,
capabilities, functions, manufacturing
release dates, and even general
availability of the product at any time.
After the above conditions have
been met, apply valid data using a
balanced code such as 8B/10B.
Frequency lock occurs within
500 µs. After frequency lock,
phase lock occurs within 2500 bit
times.
724