HDMP-1636 Datasheet, PDF (1/15 Pages) Agilent(Hewlett-Packard) – Gigabit Ethernet Transceiver Chip

Gigabit Ethernet Transceiver Chip
Preliminary Technical Data
HDMP-1636 Transceiver
HDMP-1646 Transceiver
Features
• IEEE 802.3z Gbit Ethernet
Compatible, Supports 1250
MBd Gigabit Ethernet
• Based on X3T11 “10 Bit
Specification”
• Low Power Consumption
• Transmitter and Receiver
Functions Incorporated onto
a Single IC
• Two Package Sizes
Available:
– 10 mm PQFP (HDMP-1636)
– 14 mm PQFP (HDMP-1646)
• 10-Bit Wide Parallel TTL
Compatible I/Os
• Single +3.3 V Power Supply
• 5-Volt Tolerant I/Os
• 2 KV ESD Protection
Applications
• 1250 MBd Gigabit Ethernet
Interface
• High Speed Proprietary
Interface
• Backplane Serialization
• Bus Extender
Description
The HDMP-1636/46 transceiver is
a single silicon bipolar integrated
circuit packaged in a plastic QFP
package. It provides a low-cost,
low-power physical layer solution
for 1250 MBd Gigabit Ethernet or
proprietary link interfaces. It
provides complete Serialize/
Deserialize for copper transmis-
sion, incorporating both the
Gigabit Ethernet transmit and
receive functions into a single
device.
This chip is used to build a high
speed interface (as shown in
Figure 1) while minimizing board
space, power and cost. It is
compatible with the IEEE 802.3z
specification.
The transmitter section accepts
10-bit wide parallel TTL data and
multiplexes this data into a high
speed serial data stream. The
parallel data is expected to be
8B/10B encoded data, or equiv-
alent. This parallel data is latched
into the input register of the
transmitter section on the rising
edge of the 125 MHz reference
clock (used as the transmit byte
clock).
The transmitter section’s PLL
locks to this user supplied 125
MHz byte clock. This clock is
then multiplied by 10, to gener-
ate the 1250 MHz serial signal
clock used to generate the high
speed output. The high speed
outputs are capable of interfacing
directly to copper cables for
electrical transmission or to a
separate fiber optic module for
optical transmission.
The receiver section accepts a
serial electrical data stream at
1250 MBd and recovers the
original 10-bit wide parallel data.
The receiver PLL locks onto the
incoming serial signal and
recovers the high speed serial
clock and data. The serial data is
converted back into 10-bit
parallel data, recognizing the
8B/10B comma character to
establish byte alignment.
The recovered parallel data is
presented to the user at TTL
compatible outputs. The receiver
section also recovers two 62.5
MHz receiver byte clocks which
are 180 degrees out of phase
with each other. The parallel data
is properly aligned with the rising
edge of alternating clocks.
For test purposes, the transceiver
provides for on-chip local loop-
back functionality, controlled
through an external input pin.
Additionally, the byte
(5/97)
711