HCPL-7723 Datasheet, PDF (10/12 Pages) Agilent(Hewlett-Packard) – 50 MBd 2 ns PWD High Speed CMOS Optocoupler

Application Information
Bypassing and PC Board Layout
The HCPL-7723/0723
optocouplers are extremely easy
to use. No external interface
circuitry is required because the
HCPL-7723/0723 use high-speed
CMOS IC technology allowing
CMOS logic to be connected
directly to the inputs and outputs.
As shown in Figure 1, the only
external components required for
proper operation are two bypass
capacitors. Capacitor values
should be between 0.01 µF and 0.1
µF. For each capacitor, the total
lead length between both ends of
the capacitor and the power-supply
pins should not exceed 20 mm.
Figure 2 illustrates the
recommended printed circuit
board layout for the HCPL-7723/
0723.
Propagation Delay, Pulse-Width
Distortion and Propagation Delay Skew
Propagation Delay is a figure of
merit which describes how quickly
a logic signal propagates through
a system as illustrated in Figure 3.
The propagation delay from low to
high (t_PLH) is the amount of time
required for an input signal to
propagate to the output, causing
the output to change from low to
high. Similarly, the propagation
delay from high to low (t_PHL) is
the amount of time required for
the input signal to propagate to
the output, causing the output to
change from high to low.
V_DD1
1
C1
V_I
2
NC 3
GND₁
4
8
C2
7 NC
V_DD2
6
V_O
5
GND₂
C1, C2 = 0.01 µF TO 0.1 µF
Figure 1. Functional diagram.
V_DD1
V_I
C1
GND₁
Figure 2. Recommended printed circuit board layout.
V_DD2
C2
V_O
GND₂
C1, C2 = 0.01 µF TO 0.1 µF
INPUT
V_I
OUTPUT
V_O
10%
t_PLH
90%
t_PHL
50%
90%
10%
5 V CMOS
0V
V_OH
2.5 V CMOS
V_OL
Figure 3. Timing diagram to illustrate propagation delay, tplh and tphl.
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