HX6228 Datasheet, PDF (10/12 Pages) Honeywell Solid State Electronics Center – 128K x 8 STATIC RAM-SOI HX6228

HX6228
PACKAGING
The 128K x 8 SOI SRAM is offered in a custom 32-lead or
40-lead Flat Pack. The package is constructed of multilayer
ceramic (Al₂O₃) and features internal power and ground
planes.
Ceramic chip capacitors can be mounted to the package by
the user to maximize supply noise decoupling and increase
board packing density. These capacitors effectively attach
to the internal package power and ground planes. This
design minimizes resistance and inductance of the bond
wire and package, both of which are critical in a transient
radiation environment. All NC (no connect) pins should be
connected to VSS to prevent charge build up in the
radiation environment.
32-LEAD FLAT PACK PINOUT
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
32
2
31
3
30
4
29
5
28
6
27
7
8
Top
26
25
9 ^View 24
10
23
11
22
12
21
13
20
14
19
15
18
16
17
VDD
A15
CE
NWE
A13
A8
A9
A11
NOE
A10
NCS
DQ7
DQ6
DQ5
DQ4
DQ3
40-LEAD FLAT PACK PINOUT
A16
VSS
VDD
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
NC
VDD
VSS
NC
1
40
2
39
3
38
4
37
5
36
6
35
7
34
8
33
9
32
10
31
11 ^Top 30
12 View 29
13
28
14
27
15
26
16
25
17
24
18
23
19
22
20
21
A15
VSS
VDD
NWE
CE
A13
A8
A9
A11
NOE
A10
NCS
DQ7
DQ6
DQ5
DQ4
DQ3
VDD
VSS
NC
32-LEAD FLAT PACK
E
1
22018533-001
TOP
F
VIEW
Optional capacitors
in cutout
b
Z
(width)
D
e
(pitch)
S
L
Kovar Cutout _Ceramic
Q
A
Lid [4]
Area
Body _{C Lead}
Alloy 42
V
E2
E3
VDD VSS VDD
BOTTOM
VIEW
Y
X
W
All dimensions in inches
A 0.135 ± 0.015
1
b 0.017 ± 0.002
C 0.004 to 0.009
D 0.820 ± 0.008
e 0.050 ± 0.005 [1]
E 0.600 ± 0.008
E2 0.500 ± 0.008
E3 0.040 ref
F 0.750 ± 0.005 [2]
L 0.295 min [3]
Q 0.026 to 0.045
S 0.035 ± 0.010
U U 0.080 ref
V 0.380 ref
W 0.050 ref
X 0.075 ref
Y 0.010 ref
Z 0.135 ref
[1] BSC - Basic lead spacing between centers
[2] Where lead is brazed to package
[3] Parts delivered with leads unformed
[4] Lid connected to VSS
10