HT82B42R_14 Datasheet, PDF (60/84 Pages) Holtek Semiconductor Inc – I/O MCU with USB Interface

HT82B42R/HT82B42RE
I/O MCU with USB Interface
SBCR Register
Bit
7
6
5
4
3
2
1
0
Name
CKS
M1
M0
SBEN
MLS
CSEN WCOL
TRF
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RW
POR
0
1
1
0
0
0
0
0
Bit 7
Bit 6~5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CKS: SPI clock fSPI source selection
0: fSPI=fSYS/2
1: fSPI=fSYS
M1~M0: SPI Operating Mode and baud rate control bits
00: SPI master mode; SPI clock is fSPI
01: SPI master mode; SPI clock is fSPI/4
10: SPI master mode; SPI clock is fSPI/16
11: SPI slave mode
This bit can be read or written by user software program.
SBEN: SPI serial bus enable control
0: disable
1: enable
The bit is the overall on/off control for the SPI serial bus. When the SBEN bit is
cleared to zero to disable the SPI interface, the SDI, SDO, SCK and SCS lines will
be in a floating condition and the SPI operating current will be reduced to a minimum
value. When the bit is high, the SPI interface is enabled.
MLS: SPI Data shift order
0: LSB shift first
1: MSB shift first
This is the data shift select bit and is used to select how the data is transferred, either
MSB or LSB first. Setting the bit high will select MSB first and low for LSB first.
CSEN: SPI SCS pin control
0: disable, other functions
1: enable
The CSEN bit is used as an enable/disable for the SCS pin. If this bit is low, then the
SCS pin will be disabled and placed into a floating condition. If the bit is high the SCS
pin will be enabled and used as a select pin.
Note that using the CSEN bit can be disabled or enabled by the CSEN control bit
named SPI_CSEN in the SPIR register.
WCOL: SPI Write Collision flag
0: collision free
1: collision detected
The WCOL flag is used to detect if a data collision has occurred. If this bit is high it
means that data has been attempted to be written to the SBDR register during a data
transfer operation. This writing operation will be ignored if data is being transferred.
The bit can be cleared by the application program.
TRF: SPI Transmit/Receive Complete flag
0: not complete
1: transmission/reception complete
The TRF bit is the Transmit/Receive Complete flag and is set to 1 automatically when
an SPI data transmission is completed, but must be set to 0 by the application program.
It can be used to generate an interrupt.
Rev. 1.10
60
November 05, 2014