BH66F2260 Datasheet, PDF(182/214 Page) Holtek Semiconductor Inc – R-Sensor Blood Pressure Meter Flash MCU

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BH66F2260 Datasheet, PDF (182/214 Pages) Holtek Semiconductor Inc – R-Sensor Blood Pressure Meter Flash MCU

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BH66F2260

R-Sensor Blood Pressure Meter Flash MCU

SPIA Interrupt

The Serial Peripheral Interface Interrupt, also known as the SPIA interrupt, will take place when the

SPIA Interrupt request flag, SPIAF, is set, which occurs when a byte of data has been received or

transmitted by the SPIA interface or an SPIA incomplete transfer occurs. To allow the program to

branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and the Serial

Interface Interrupt enable bit, SPIAE, must first be set. When the interrupt is enabled, the stack is

not full and any of the above described situations occurs, a subroutine call to the respective Interrupt

vector, will take place. When the interrupt is serviced, the Serial Interface Interrupt flag, SPIAF, will

be automatically cleared. The EMI bit will also be automatically cleared to disable other interrupts.

Time Base Interrupts

The function of the Time Base Interrupts is to provide regular time signal in the form of an internal

interrupt. They are controlled by the overflow signals from their respective timer functions. When

these happens their respective interrupt request flags, TB0F or TB1F will be set. To allow the

program to branch to their respective interrupt vector addresses, the global interrupt enable bit, EMI

and Time Base enable bits, TB0E or TB1E, must first be set. When the interrupt is enabled, the stack

is not full and the Time Base overflows, a subroutine call to their respective vector locations will

take place. When the interrupt is serviced, the respective interrupt request flag, TB0F or TB1F, will

be automatically reset and the EMI bit will be cleared to disable other interrupts.

The Time Base clock source, fPSC, originates from the internal clock source fSYS, fSYS/4 or fSUB

and then passes through a divider, the division ratio of which is selected by programming the

appropriate bits in the TB0C and TB1C registers to obtain longer interrupt periods whose value

ranges. The clock source which in turn controls the Time Base interrupt period is selected using the

CLKSEL1~CLKSEL0 bits in the PSCR register.

fSYS

fSYS/4

fSUB

fPSC

CLKSEL[1:0]

Prescaler

TB0ON

fPSC/28 ~ fPSC/215

TB0[2:0]

fPSC/28 ~ fPSC/215

TB1ON

Time Base Interrupts

TB1[2:0]

Time Base 0 Interrupt

Time Base 1 Interrupt

PSCR Register

Bit

Name

R/W

POR

Bit 7~2

Bit 1~0

Unimplemented, read as "0"

CLKSEL1~CLKSEL0: Prescaler clock source selection

00: fSYS

01: fSYS/4

1x: fSUB

CLKSEL1 CLKSEL0

R/W

Rev. 1.00

182

March 15, 2017

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