BH66F2260 Datasheet, PDF (150/214 Pages) Holtek Semiconductor Inc – R-Sensor Blood Pressure Meter Flash MCU

BH66F2260
R-Sensor Blood Pressure Meter Flash MCU
• SPIAC0 Register
Bit
7
6
5
4
3
2
1
0
Name SASPI2 SASPI1 SASPI0
—
—
—
SPIAEN SPIAICF
R/W
R/W
R/W
R/W
—
—
—
R/W
R/W
POR
1
1
1
—
—
—
0
0
Bit 7~5
Bit 4~2
Bit 1
Bit 0
SASPI2~SASPI0: SPIA Operating Mode Control
000: SPIA master mode; SPIA clock is fSYS/4
001: SPIA master mode; SPIA clock is fSYS/16
010: SPIA master mode; SPIA clock is fSYS/64
011: SPIA master mode; SPIA clock is fSUB
100: SPIA master mode; SPIA clock is PTM1 CCRP match frequency/2
101: SPIA slave mode
110: Unimplemented
111: Unimplemented
These bits are used to control the SPIA Master/Slave selection and the SPIA Master
clock frequency. The SPIA clock is a function of the system clock but can also be
chosen to be sourced from PTM1 and fSUB. If the SPIA Slave Mode is selected then the
clock will be supplied by an external Master device.
Unimplemented, read as "0"
SPIAEN: SPIA Enable Control
0: Disable
1: Enable
The bit is the overall on/off control for the SPIA interface. When the SPIAEN bit
is cleared to zero to disable the SPIA interface, the SDIA, SDOA, SCKA and SCSA
lines will lose their SPIA function and the SPIA operating current will be reduced to a
minimum value. When the bit is high the SPIA interface is enabled.
SPIAICF: SPIA Incomplete Flag
0: SPIA incomplete condition is not occurred
1: SPIA incomplete condition is occured
This bit is only available when the SPIA is configured to operate in an SPIA slave
mode. If the SPIA operates in the slave mode with the SPIAEN and SACSEN bits
both being set to 1 but the SCSA line is pulled high by the external master device
before the SPIA data transfer is completely finished, the SPIAICF bit will be set to 1
together with the SATRF bit. When this condition occurs, the corresponding interrupt
will occur if the interrupt function is enabled. However, the SATRF bit will not be set
to 1 if the SPIAICF bit is set to 1 by software application program.
• SPIAC1 Register
Bit
7
Name
—
R/W
—
POR
—
6
5
4
3
2
1
0
— SACKPOLB SACKEG SAMLS SACSEN SAWCOL SATRF
—
R/W
R/W
R/W
R/W
R/W
R/W
—
0
0
0
0
0
0
Bit 7~6
Bit 5
Unimplemented, read as "0".
SACKPOLB: SPIA clock line base condition selection
0: The SCKA line will be high when the clock is inactive
1: The SCKA line will be low when the clock is inactive
The SACKPOLB bit determines the base condition of the clock line, if the bit is high,
then the SCKA line will be low when the clock is inactive. When the SACKPOLB bit
is low, then the SCKA line will be high when the clock is inactive.
Rev. 1.00
150
March 15, 2017