HD404054 Datasheet, PDF (9/101 Pages) Hitachi Semiconductor – HMCS400-series microcomputers designed to increase program productivity with large-capacity memory

HD404054 Series/HD404094 Series
Bit 3
IM0
0
(IM of INT₀)
Bit 2
IF0
(IF of INT₀)
Bit 1
RSP
(Reset SP bit)
1
IMTA
(IM of timer A)
IFTA
(IF of timer A)
IM1
(IM of INT₁)
Bit 0
IE
(Interrupt
enable flag)
IF1
(IF of INT₁)
$000
$001
2
IMTC
(IM of timer C)
IFTC
(IF of timer C)
Not used
Not used
$002
IMS1
3
(IM of serial
interface 1)
IFS1
(IF of serial
interface 1)
IMTD
(IM of timer D)
IFTD
(IF of timer D)
$003
Interrupt control bits area
Bit 3
32
Not used
RAME
33 (RAM enable
flag)
Bit 2
Bit 1
Not used
WDON
(Watchdog
on flag)
Not used
ICEF
(Input capture
error flag)
Register flag area
Bit 0
Not used
ICSF
(Input capture
status flag)
$020
$021
IF: Interrupt request flag
IM: Interrupt mask
IE: Interrupt enable flag
SP: Stack pointer
Figure 3 Configuration of Interrupt Control Bits and Register Flag Areas
IE
IM
IF
ICSF
ICEF
RAME
RSP
WDON
Not used
SEM/SEMD
Allowed
Not executed
Not executed
Allowed
Not executed
REM/REMD
Allowed
Allowed
Allowed
Not executed
Not executed
TM/TMD
Allowed
Allowed
Inhibited
Inhibited
Inhibited
Note: WDON is reset by MCU reset or by STOPC enable for stop mode cancellation.
If the TM or TDM instruction is executed for the inhibited bits or non-existing bits,
the value in ST becomes invalid.
Figure 4 Usage Limitations of RAM Bit Manipulation Instructions
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